Matching Items (3)
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- All Subjects: Semiconductors
- Genre: Doctoral Dissertation
- Creators: Alford, Terry
Description
The aging process due to Bias Temperature Instability (both NBTI and PBTI) and Channel Hot Carrier (CHC) is a key limiting factor of circuit lifetime in CMOS design. Threshold voltage shift due to BTI is a strong function of stress voltage and temperature complicating stress and recovery prediction. This poses a unique challenge for long-term aging prediction for wide range of stress patterns. Traditional approaches usually resort to an average stress waveform to simplify the lifetime prediction. They are efficient, but fail to capture circuit operation, especially under dynamic voltage scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. This work presents a suite of modelling solutions for BTI that enable aging simulation under all possible stress conditions. Key features of this work are compact models to predict BTI aging based on Reaction-Diffusion theory when the stress voltage is varying. The results to both reaction-diffusion (RD) and trapping-detrapping (TD) mechanisms are presented to cover underlying physics. Silicon validation of these models is performed at 28nm, 45nm and 65nm technology nodes, at both device and circuit levels. Efficient simulation leveraging the BTI models under DVS and random input waveform is applied to both digital and analog representative circuits such as ring oscillators and LNA. Both physical mechanisms are combined into a unified model which improves prediction accuracy at 45nm and 65nm nodes. Critical failure condition is also illustrated based on NBTI and PBTI at 28nm. A comprehensive picture for duty cycle shift is shown. DC stress under clock gating schemes results in monotonic shift in duty cycle which an AC stress causes duty cycle to converge close to 50% value. Proposed work provides a general and comprehensive solution to aging analysis under random stress patterns under BTI.
Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.
Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.
ContributorsSutaria, Ketul (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Chakrabarti, Chaitali (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2014
Description
The goal of this work is to develop low cost and highly efficient hybrid solar cells based on semiconductor nanoparticles (NPs). Hybrid solar cells have been demonstrated to take advantages of both inorganic and organic semiconductors by employing simple soluble process. In order to improve the power conversion efficiency (PCE), the bulk heterojunction (BHJ) of cadmium selenide (CdSe) tetrapods (TPs) and poly (3-hexylthiophene) (P3HT) are introduced as an electron acceptor and donor, respectively. The dimension of CdSe TPs and the 3D spatial distribution of CdSe TPs:P3HT photoactive blends are investigated to improve optical and electrical properties of photovoltaic devices. Hybrid solar cells having long-armed CdSe TPs and P3HT establish higher PCE of 1.12% when compared to device employing short-armed TPs of 0.80%. The device performance are improved by using longer armed CdSe TPs, which aids in better percolation connectivity and reduced charge hopping events, thus leading to better charge transport. The device architecture of hybrid solar cells is examined to assist vertical phase separation (VPS). Improvement of VPS in hybrid solar cells using CdSe TPs:P3HT photoactive blends is systematically manipulated by solution processed interfacial layers, resulting in enhanced device performance. Multi-layered hybrid solar cells assist better light absorption, efficient charge carrier transport, and increase of the surface contact area. In this work, hole transport assisting layer (HTAL)/BHJ photoactive layer (BPL)/electron transport assisting layer (ETAL) or HTAL/BPL/ETAL (HBE) multi-layered structure is introduced, similarly to p-type layer/intermixed photoactive layer
-type layer (p-i-n) structure of organic photovoltaic devices. To further control the improvement of the device performance, the effects of nano-scale morphology from solvents having different boiling points, the various shapes of semiconductor NPs, and the emergence of blending NPs are demonstrated. The formation of favorable 3D networks in photoactive layer is attributed to enhance the efficient charge transport by the optimized combination of semiconductor NPs in polymer matrix.
-type layer (p-i-n) structure of organic photovoltaic devices. To further control the improvement of the device performance, the effects of nano-scale morphology from solvents having different boiling points, the various shapes of semiconductor NPs, and the emergence of blending NPs are demonstrated. The formation of favorable 3D networks in photoactive layer is attributed to enhance the efficient charge transport by the optimized combination of semiconductor NPs in polymer matrix.
ContributorsLee, Kyu Sung (Author) / Jabbour, Ghassan E. (Thesis advisor) / Alford, Terry (Thesis advisor) / Krause, Stephen (Committee member) / Arizona State University (Publisher)
Created2012
Description
Wide bandgap semiconductors are of much current interest due to their superior electrical properties. This dissertation describes electron microscopy characterization of GaN-on-GaN structures for high-power vertical device applications. Unintentionally-doped (UID) GaN layers grown homoepitaxially via metal-organic chemical vapor deposition on freestanding GaN substrates, were subjected to dry etching, and layers of UID-GaN/p-GaN were over-grown. The as-grown and regrown heterostructures were examined in cross-section using transmission electron microscopy (TEM). Two different etching treatments, fast-etch-only and multiple etches with decreasing power, were employed. The fast-etch-only devices showed GaN-on-GaN interface at etched location, and low device breakdown voltages were measured (~ 45-95V). In comparison, no interfaces were visible after multiple etching steps, and the corresponding breakdown voltages were much higher (~1200-1270V). These results emphasized importance of optimizing surface etching techniques for avoiding degraded device performance.
The morphology of GaN-on-GaN devices after reverse-bias electrical stressing to breakdown was investigated. All failed devices had irreversible structural damage, showing large surface craters (~15-35 microns deep) with lengthy surface cracks. Cross-sectional TEM of failed devices showed high densities of threading dislocations (TDs) around the cracks and near crater surfaces. Progressive ion-milling across damaged devices revealed high densities of TDs and the presence of voids beneath cracks: these features were not observed in unstressed devices. The morphology of GaN substrates grown by hydride vapor-phase epitaxy (HVPE) and by ammonothermal methods were correlated with reverse-bias results. HVPE substrates showed arrays of surface features when observed by X-ray topography (XRT). All fabricated devices that overlapped with these features had typical reverse-bias voltages less than 100V at a leakage current limit of 10-6 A. In contrast, devices not overlapping with such features reached voltages greater than 300V. After etching, HVPE substrate surfaces showed defect clusters and macro-pits, whereas XRT images of ammonothermal substrate revealed no visible features. However, some devices fabricated on ammonothermal substrate failed at low voltages. Devices on HVPE and ammonothermal substrates with low breakdown voltages showed crater-like surface damage and revealed TDs (~25µm deep) and voids; such features were not observed in devices reaching higher voltages. These results should assist in developing protocols to fabricate reliable high-voltage devices.
ContributorsPeri, Prudhvi Ram (Author) / Smith, David J. (Thesis advisor) / Alford, Terry (Committee member) / Mccartney, Martha R (Committee member) / Nemanich, Robert (Committee member) / Zhao, Yuji (Committee member) / Arizona State University (Publisher)
Created2021