Matching Items (7)
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- All Subjects: Semiconductors
- Creators: Simonson, Mark
Description
Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature. Therefore, the objective of this research was to characterize the electromigration lifetimes of passivated Au interconnects under precisely controlled stress conditions with statistically relevant quantities to obtain accurate model parameters essential for extrapolation to normal operational conditions. This research objective was accomplished through measurement of electromigration lifetimes of large quantities of passivated electroplated Au interconnects utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures. A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 ìm. All Au lifetime distributions followed log-normal distributions and Black's model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time.
ContributorsKilgore, Stephen (Author) / Adams, James (Thesis advisor) / Schroder, Dieter (Thesis advisor) / Krause, Stephen (Committee member) / Gaw, Craig (Committee member) / Arizona State University (Publisher)
Created2013
Description
This dissertation addresses challenges pertaining to multi-junction (MJ) solar cells from material development to device design and characterization. Firstly, among the various methods to improve the energy conversion efficiency of MJ solar cells using, a novel approach proposed recently is to use II-VI (MgZnCd)(SeTe) and III-V (AlGaIn)(AsSb) semiconductors lattice-matched on GaSb or InAs substrates for current-matched subcells with minimal defect densities. CdSe/CdTe superlattices are proposed as a potential candidate for a subcell in the MJ solar cell designs using this material system, and therefore the material properties of the superlattices are studied. The high structural qualities of the superlattices are obtained from high resolution X-ray diffraction measurements and cross-sectional transmission electron microscopy images. The effective bandgap energies of the superlattices obtained from the photoluminescence (PL) measurements vary with the layer thicknesses, and are smaller than the bandgap energies of either the constituent material. Furthermore, The PL peak position measured at the steady state exhibits a blue shift that increases with the excess carrier concentration. These results confirm a strong type-II band edge alignment between CdSe and CdTe. The valence band offset between unstrained CdSe and CdTe is determined as 0.63 eV±0.06 eV by fitting the measured PL peak positions using the Kronig-Penney model. The blue shift in PL peak position is found to be primarily caused by the band bending effect based on self-consistent solutions of the Schrödinger and Poisson equations. Secondly, the design of the contact grid layout is studied to maximize the power output and energy conversion efficiency for concentrator solar cells. Because the conventional minimum power loss method used for the contact design is not accurate in determining the series resistance loss, a method of using a distributed series resistance model to maximize the power output is proposed for the contact design. It is found that the junction recombination loss in addition to the series resistance loss and shadowing loss can significantly affect the contact layout. The optimal finger spacing and maximum efficiency calculated by the two methods are close, and the differences are dependent on the series resistance and saturation currents of solar cells. Lastly, the accurate measurements of external quantum efficiency (EQE) are important for the design and development of MJ solar cells. However, the electrical and optical couplings between the subcells have caused EQE measurement artifacts. In order to interpret the measurement artifacts, DC and small signal models are built for the bias condition and the scan of chopped monochromatic light in the EQE measurements. Characterization methods are developed for the device parameters used in the models. The EQE measurement artifacts are found to be caused by the shunt and luminescence coupling effects, and can be minimized using proper voltage and light biases. Novel measurement methods using a pulse voltage bias or a pulse light bias are invented to eliminate the EQE measurement artifacts. These measurement methods are nondestructive and easy to implement. The pulse voltage bias or pulse light bias is superimposed on the conventional DC voltage and light biases, in order to control the operating points of the subcells and counterbalance the effects of shunt and luminescence coupling. The methods are demonstrated for the first time to effectively eliminate the measurement artifacts.
ContributorsLi, Jingjing (Author) / Zhang, Yong-Hang (Thesis advisor) / Tao, Meng (Committee member) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2012
Description
The purpose of this thesis was to design a market entrance strategy for Company X to enter the microcontroller (MCU) market within the Internet of Things (IoT). The five IoT segments are automotive; medical; retail; industrial; and military, aerospace, and government. To reach a final decision, we will research the markets, analyze make versus buy scenarios, and deliver a financial analysis on the chosen strategy. Based on the potential financial benefits and compatibility with Company X's current business model, we recommend that Company X enter the automotive segment through mergers & acquisitions (M&A). After analyzing the supply chain structure of the automotive IoT, we advise Company X to acquire Freescale Semiconductor for $46.98 per share.
ContributorsBradley, Rachel (Co-author) / Fankhauser, Elisa (Co-author) / McCoach, Robert (Co-author) / Zheng, Weilin (Co-author) / Simonson, Mark (Thesis director) / Hertzel, Mike (Committee member) / Barrett, The Honors College (Contributor) / Department of Finance (Contributor) / Department of Supply Chain Management (Contributor) / School of Accountancy (Contributor) / School of International Letters and Cultures (Contributor) / WPC Graduate Programs (Contributor)
Created2015-05
Description
Company X is one of the world's largest semiconductor companies in the world, having a current market capitalization of 177.44 Billion USD, an enterprise value of 173.6 Billion USD, and generated 52.7 billion USD in revenue in fiscal year 2013. Recently, Company X has been looking to expand its Foundry business. The Foundry business in the semiconductor business is the actual process of making the chips. This process can be approached in several different ways by companies who need their chips built. A company, like TSMC, can be considered a pure-play company and only makes chips for other companies. A fabless company, like Apple, creates its own chip design and then allows another company to build them. It also uses other chip designs for its products, but outsources the building to another company. Lastly, the integrated device manufacturing companies like Samsung or Company X both design and build the chip. The foundry industry is a rather novel market for Company X because it owns less than 1 percent of the market. However, the industry itself is rather large, generating a total of 40 billion dollars in revenue annually, with expectations to have increasing year over year growth into the foreseeable future. The industry is fairly concentrated with TSMC being the top competitor, owning roughly 50 percent of the market with Samsung and Global Foundries lagging behind as notable competitors. It is a young industry and there is potential opportunity for companies that want to get into the business. For Company X, it is not only another market to get into, but also an added business segment to supplant their business segments that are forecasted to do poorly in the near future. This thesis will analyze the financial opportunity for Company X in the foundry space. Our final product is a series of P&L's which illustrate our findings. The results of our analysis were presented and defended in front of a panel of Company X managers and executives.
ContributorsJones, Trevor (Author) / Matiski, Matthew (Co-author) / Green, Alex (Co-author) / Simonson, Mark (Thesis director) / Hertzel, Michael (Committee member) / Department of Finance (Contributor) / W. P. Carey School of Business (Contributor) / Barrett, The Honors College (Contributor)
Created2015-05
Description
Our thesis project aims to evaluate a major semiconductor company's (The Company) substrate supplier strategy in order to find the ideal number of suppliers that minimizes fixed cost and supplier power. With The Company spending roughly $2.2 billion annually on substrates, supplier strategy has a significant impact on their costs. As a general rule in micro processing, the circuitry of the processor becomes twice as dense every two years. The substrate, being the pathway through which the process or with the motherboard, must become more advanced as well, although the technology does not grow at nearly the same speed. Leading the way in their industry, The Company is at the forefront of technology and produces the world's most advanced processing units. The suppliers The Company purchases from must be innovators in their own respective fields in order to be capable of handling such "bleeding-edge" technology; this requires a supplier to make a commitment to continuously work towards meeting The Company's constantly changing technological requirements. The ultimate goal of this project is to determine the ideal number of substrate suppliers that balances the effects of production costs and buying power to give the company the best overall purchase price.
ContributorsWright, Brian (Author) / Hertzel, Michael (Thesis director) / Simonson, Mark (Committee member) / Shirts, John (Committee member) / Barrett, The Honors College (Contributor)
Created2012-05
Description
We gathered and analyzed key data from a wide-range of competitors in the foundry, fabless, and Integrated design manufacturing business. After detecting a downward trend in the return of invested capital (ROIC) and higher capital intensity of Company X, we searched for alternatives to turn this around. We conclude that, to decrease the net PPE of Company X, a sale-leaseback transaction would help Company X reduce their balance sheet and provided financing to advance their manufacturing capabilities.
ContributorsBhat, Arjun Khandige (Co-author) / Brock, Ethan (Co-author) / Gamperl, Max (Co-author) / Gupta, Viraj (Co-author) / Macha, Sanketh (Co-author) / Simonson, Mark (Thesis director) / Duran, Juan Carlos (Committee member) / Department of Finance (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
This paper serves as an analysis of the current operational conditions of a real-world company – referred to as “Company X” – with respect to the IC substrate industry. The cost of substrates, a crucial component in the production of Company X’s product, has recently diverged from Company X’s predictions and is contributing to declining profitability. This analysis aims to discover the underlying cause for price divergence and recommend potential resolutions to improve the forecast of substrate costs and profitability. The paper is organized as follows: Chapter 1 is an introduction to IC substrates and the industry as a whole, Chapter 2 is a breakdown of the specific factors responsible for substrate prices, and Chapter 3 delivers a final recommendation to Company X and concludes the paper.
ContributorsFares, Ariya (Ari) (Author) / O’Loughlin, Connor (Co-author) / Guillaume, Riley (Co-author) / Aggarwal, Bianca (Co-author) / King, Camden (Co-author) / Simonson, Mark (Thesis director) / Hertzel, Michael (Committee member) / Barrett, The Honors College (Contributor) / Department of Finance (Contributor)
Created2023-05