Matching Items (8)
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- All Subjects: Semiconductors
- All Subjects: MESFET
- Creators: Drucker, Jeffery
- Creators: Schroder, Dieter
Description
Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature. Therefore, the objective of this research was to characterize the electromigration lifetimes of passivated Au interconnects under precisely controlled stress conditions with statistically relevant quantities to obtain accurate model parameters essential for extrapolation to normal operational conditions. This research objective was accomplished through measurement of electromigration lifetimes of large quantities of passivated electroplated Au interconnects utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures. A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 ìm. All Au lifetime distributions followed log-normal distributions and Black's model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time.
ContributorsKilgore, Stephen (Author) / Adams, James (Thesis advisor) / Schroder, Dieter (Thesis advisor) / Krause, Stephen (Committee member) / Gaw, Craig (Committee member) / Arizona State University (Publisher)
Created2013
Description
This dissertation presents research findings on the three materials systems: lateral Si nanowires (SiNW), In2Se3/Bi2Se3 heterostructures and graphene. The first part of the thesis was focused on the growth and characterization of lateral SiNW. Lateral here refers to wires growing along the plane of substrate; vertical NW on the other hand grow out of the plane of substrate. It was found, using the Au-seeded vapor – liquid – solid technique, that epitaxial single-crystal SiNW can be grown laterally along Si(111) substrates that have been miscut toward [11− 2]. The ratio of lateral-to-vertical NW was found to increase as the miscut angle increased and as disilane pressure and substrate temperature decreased. Based on this observation, growth parameters were identified whereby all of the deposited Au seeds formed lateral NW. Furthermore, the nanofaceted substrate guided the growth via a mechanism that involved pinning of the trijunction at the liquid/solid interface of the growing nanowire.
Next, the growth of selenide heterostructures was explored. Specifically, molecular beam epitaxy was utilized to grow In2Se3 and Bi2Se3 films on h-BN, highly oriented pyrolytic graphite and Si(111) substrates. Growth optimizations of In2Se3 and Bi2Se3 films were carried out by systematically varying the growth parameters. While the growth of these films was demonstrated on h-BN and HOPG surface, the majority of the effort was focused on growth on Si(111). Atomically flat terraces that extended laterally for several hundred nm, which were separated by single quintuple layer high steps characterized surface of the best In2Se3 films grown on Si(111). These In2Se3 films were suitable for subsequent high quality epitaxy of Bi2Se3 .
The last part of this dissertation was focused on a recently initiated and ongoing study of graphene growth on liquid metal surfaces. The initial part of the study comprised a successful modification of an existing growth system to accommodate graphene synthesis and process development for reproducible graphene growth. Graphene was grown on Cu, Au and AuCu alloys at varioua conditions. Preliminary results showed triangular features on the liquid part of the Cu metal surface. For Au, and AuCu alloys, hexagonal features were noticed both on the solid and liquid parts.
Next, the growth of selenide heterostructures was explored. Specifically, molecular beam epitaxy was utilized to grow In2Se3 and Bi2Se3 films on h-BN, highly oriented pyrolytic graphite and Si(111) substrates. Growth optimizations of In2Se3 and Bi2Se3 films were carried out by systematically varying the growth parameters. While the growth of these films was demonstrated on h-BN and HOPG surface, the majority of the effort was focused on growth on Si(111). Atomically flat terraces that extended laterally for several hundred nm, which were separated by single quintuple layer high steps characterized surface of the best In2Se3 films grown on Si(111). These In2Se3 films were suitable for subsequent high quality epitaxy of Bi2Se3 .
The last part of this dissertation was focused on a recently initiated and ongoing study of graphene growth on liquid metal surfaces. The initial part of the study comprised a successful modification of an existing growth system to accommodate graphene synthesis and process development for reproducible graphene growth. Graphene was grown on Cu, Au and AuCu alloys at varioua conditions. Preliminary results showed triangular features on the liquid part of the Cu metal surface. For Au, and AuCu alloys, hexagonal features were noticed both on the solid and liquid parts.
ContributorsRathi, Somilkumar J (Author) / Drucker, Jeffery (Thesis advisor) / Smith, David (Committee member) / Chen, Tingyong (Committee member) / Arizona State University (Publisher)
Created2014
Description
Off-axis electron holography (EH) has been used to characterize electrostatic potential, active dopant concentrations and charge distribution in semiconductor nanostructures, including ZnO nanowires (NWs) and thin films, ZnTe thin films, Si NWs with axial p-n junctions, Si-Ge axial heterojunction NWs, and Ge/LixGe core/shell NW.
The mean inner potential (MIP) and inelastic mean free path (IMFP) of ZnO NWs have been measured to be 15.3V±0.2V and 55±3nm, respectively, for 200keV electrons. These values were then used to characterize the thickness of a ZnO nano-sheet and gave consistent values. The MIP and IMFP for ZnTe thin films were measured to be 13.7±0.6V and 46±2nm, respectively, for 200keV electrons. A thin film expected to have a p-n junction was studied, but no signal due to the junction was observed. The importance of dynamical effects was systematically studied using Bloch wave simulations.
The built-in potentials in Si NWs across the doped p-n junction and the Schottky junction due to Au catalyst were measured to be 1.0±0.3V and 0.5±0.3V, respectively. Simulations indicated that the dopant concentrations were ~1019cm-3 for donors and ~1017 cm-3 for acceptors. The effects of positively charged Au catalyst, a possible n+-n--p junction transition region and possible surface charge, were also systematically studied using simulations.
Si-Ge heterojunction NWs were studied. Dopant concentrations were extracted by atom probe tomography. The built-in potential offset was measured to be 0.4±0.2V, with the Ge side lower. Comparisons with simulations indicated that Ga present in the Si region was only partially activated. In situ EH biasing experiments combined with simulations indicated the B dopant in Ge was mostly activated but not the P dopant in Si. I-V characteristic curves were measured and explained using simulations.
The Ge/LixGe core/shell structure was studied during lithiation. The MIP for LixGe decreased with time due to increased Li content. A model was proposed to explain the lower measured Ge potential, and the trapped electron density in Ge core was calculated to be 3×1018 electrons/cm3. The Li amount during lithiation was also calculated using MIP and volume ratio, indicating that it was lower than the fully lithiated phase.
The mean inner potential (MIP) and inelastic mean free path (IMFP) of ZnO NWs have been measured to be 15.3V±0.2V and 55±3nm, respectively, for 200keV electrons. These values were then used to characterize the thickness of a ZnO nano-sheet and gave consistent values. The MIP and IMFP for ZnTe thin films were measured to be 13.7±0.6V and 46±2nm, respectively, for 200keV electrons. A thin film expected to have a p-n junction was studied, but no signal due to the junction was observed. The importance of dynamical effects was systematically studied using Bloch wave simulations.
The built-in potentials in Si NWs across the doped p-n junction and the Schottky junction due to Au catalyst were measured to be 1.0±0.3V and 0.5±0.3V, respectively. Simulations indicated that the dopant concentrations were ~1019cm-3 for donors and ~1017 cm-3 for acceptors. The effects of positively charged Au catalyst, a possible n+-n--p junction transition region and possible surface charge, were also systematically studied using simulations.
Si-Ge heterojunction NWs were studied. Dopant concentrations were extracted by atom probe tomography. The built-in potential offset was measured to be 0.4±0.2V, with the Ge side lower. Comparisons with simulations indicated that Ga present in the Si region was only partially activated. In situ EH biasing experiments combined with simulations indicated the B dopant in Ge was mostly activated but not the P dopant in Si. I-V characteristic curves were measured and explained using simulations.
The Ge/LixGe core/shell structure was studied during lithiation. The MIP for LixGe decreased with time due to increased Li content. A model was proposed to explain the lower measured Ge potential, and the trapped electron density in Ge core was calculated to be 3×1018 electrons/cm3. The Li amount during lithiation was also calculated using MIP and volume ratio, indicating that it was lower than the fully lithiated phase.
ContributorsGan, Zhaofeng (Author) / Mccartney, Martha R (Thesis advisor) / Smith, David J. (Thesis advisor) / Drucker, Jeffery (Committee member) / Bennett, Peter A (Committee member) / Arizona State University (Publisher)
Created2015
Description
There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.
ContributorsSochacki, John (Author) / Thornton, Trevor J (Thesis advisor) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Description
This dissertation addresses challenges pertaining to multi-junction (MJ) solar cells from material development to device design and characterization. Firstly, among the various methods to improve the energy conversion efficiency of MJ solar cells using, a novel approach proposed recently is to use II-VI (MgZnCd)(SeTe) and III-V (AlGaIn)(AsSb) semiconductors lattice-matched on GaSb or InAs substrates for current-matched subcells with minimal defect densities. CdSe/CdTe superlattices are proposed as a potential candidate for a subcell in the MJ solar cell designs using this material system, and therefore the material properties of the superlattices are studied. The high structural qualities of the superlattices are obtained from high resolution X-ray diffraction measurements and cross-sectional transmission electron microscopy images. The effective bandgap energies of the superlattices obtained from the photoluminescence (PL) measurements vary with the layer thicknesses, and are smaller than the bandgap energies of either the constituent material. Furthermore, The PL peak position measured at the steady state exhibits a blue shift that increases with the excess carrier concentration. These results confirm a strong type-II band edge alignment between CdSe and CdTe. The valence band offset between unstrained CdSe and CdTe is determined as 0.63 eV±0.06 eV by fitting the measured PL peak positions using the Kronig-Penney model. The blue shift in PL peak position is found to be primarily caused by the band bending effect based on self-consistent solutions of the Schrödinger and Poisson equations. Secondly, the design of the contact grid layout is studied to maximize the power output and energy conversion efficiency for concentrator solar cells. Because the conventional minimum power loss method used for the contact design is not accurate in determining the series resistance loss, a method of using a distributed series resistance model to maximize the power output is proposed for the contact design. It is found that the junction recombination loss in addition to the series resistance loss and shadowing loss can significantly affect the contact layout. The optimal finger spacing and maximum efficiency calculated by the two methods are close, and the differences are dependent on the series resistance and saturation currents of solar cells. Lastly, the accurate measurements of external quantum efficiency (EQE) are important for the design and development of MJ solar cells. However, the electrical and optical couplings between the subcells have caused EQE measurement artifacts. In order to interpret the measurement artifacts, DC and small signal models are built for the bias condition and the scan of chopped monochromatic light in the EQE measurements. Characterization methods are developed for the device parameters used in the models. The EQE measurement artifacts are found to be caused by the shunt and luminescence coupling effects, and can be minimized using proper voltage and light biases. Novel measurement methods using a pulse voltage bias or a pulse light bias are invented to eliminate the EQE measurement artifacts. These measurement methods are nondestructive and easy to implement. The pulse voltage bias or pulse light bias is superimposed on the conventional DC voltage and light biases, in order to control the operating points of the subcells and counterbalance the effects of shunt and luminescence coupling. The methods are demonstrated for the first time to effectively eliminate the measurement artifacts.
ContributorsLi, Jingjing (Author) / Zhang, Yong-Hang (Thesis advisor) / Tao, Meng (Committee member) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2012
Description
ABSTRACT Group III-nitride semiconductor materials have been commercially used in fabrication of light-emitting diodes (LEDs) and laser diodes (LDs) covering the spectral range from UV to visible and infrared, and exhibit unique properties suitable for modern optoelectronic applications. Great advances have recently happened in the research and development in high-power and high-efficiency blue-green-white LEDs, blue LDs and other optoelectronic applications. However, there are still many unsolved challenges with these materials. In this dissertation, several issues concerning structural, electronic and optical properties of III-nitrides have been investigated using a combination of transmission electron microscopy (TEM), electron holography (EH) and cathodoluminescence (CL) techniques. First, a trend of indium chemical inhomogeneity has been found as the indium composition increases for the InGaN epitaxial layers grown by hydride vapor phase epitaxy. Second, different mechanisms contributing to the strain relaxation have been studied for non-polar InGaN epitaxial layers grown on zinc oxide (ZnO) substrate. Third, various structural morphologies of non-polar InGaN epitaxial layers grown on free-standing GaN substrate have been investigated. Fourth, the effect of the growth temperature on the performance of GaN lattice-matched InAlN electron blocking layers has been studied. Finally, the electronic and optical properties of GaN nanowires containing a AlN/GaN superlattice structure have been investigated showing relatively small internal electric field and superlattice- and defect-related emissions along the nanowires.
ContributorsSun, Kewei (Author) / Ponce, Fernando (Thesis advisor) / Smith, David (Committee member) / Treacy, Michael (Committee member) / Drucker, Jeffery (Committee member) / Schmidt, Kevin (Committee member) / Arizona State University (Publisher)
Created2011
Description
The research of this dissertation involved quantitative characterization of electrostatic potential and charge distribution of semiconductor nanostructures using off-axis electron holography, as well as other electron microscopy techniques. The investigated nanostructures included Ge quantum dots, Ge/Si core/shell nanowires, and polytype heterostructures in ZnSe nanobelts. Hole densities were calculated for the first two systems, and the spontaneous polarization for wurtzite ZnSe was determined. Epitaxial Ge quantum dots (QDs) embedded in boron-doped silicon were studied. Reconstructed phase images showed extra phase shifts near the base of the QDs, which was attributed to hole accumulation in these regions. The resulting charge density was (0.03±0.003) holes
m3, which corresponded to about 30 holes localized to a pyramidal, 25-nm-wide Ge QD. This value was in reasonable agreement with the average number of holes confined to each Ge dot determined using a capacitance-voltage measurement. Hole accumulation in Ge/Si core/shell nanowires was observed and quantified using off-axis electron holography and other electron microscopy techniques. High-angle annular-dark-field scanning transmission electron microscopy images and electron holograms were obtained from specific nanowires. The intensities of the former were utilized to calculate the projected thicknesses for both the Ge core and the Si shell. The excess phase shifts measured by electron holography across the nanowires indicated the presence of holes inside the Ge cores. The hole density in the core regions was calculated to be (0.4±0.2)
m3 based on a simplified coaxial cylindrical model. Homogeneous zincblende/wurtzite heterostructure junctions in ZnSe nanobelts were studied. The observed electrostatic fields and charge accumulation were attributed to spontaneous polarization present in the wurtzite regions since the contributions from piezoelectric polarization were shown to be insignificant based on geometric phase analysis. The spontaneous polarization for the wurtzite ZnSe was calculated to be psp = -(0.0029±0.00013) C/m2, whereas a first principles' calculation gave psp = -0.0063 C/m2. The atomic arrangements and polarity continuity at the zincblende/wurtzite interface were determined through aberration-corrected high-angle annular-dark-field imaging, which revealed no polarity reversal across the interface. Overall, the successful outcomes of these studies confirmed the capability of off-axis electron holography to provide quantitative electrostatic information for nanostructured materials.
m3, which corresponded to about 30 holes localized to a pyramidal, 25-nm-wide Ge QD. This value was in reasonable agreement with the average number of holes confined to each Ge dot determined using a capacitance-voltage measurement. Hole accumulation in Ge/Si core/shell nanowires was observed and quantified using off-axis electron holography and other electron microscopy techniques. High-angle annular-dark-field scanning transmission electron microscopy images and electron holograms were obtained from specific nanowires. The intensities of the former were utilized to calculate the projected thicknesses for both the Ge core and the Si shell. The excess phase shifts measured by electron holography across the nanowires indicated the presence of holes inside the Ge cores. The hole density in the core regions was calculated to be (0.4±0.2)
m3 based on a simplified coaxial cylindrical model. Homogeneous zincblende/wurtzite heterostructure junctions in ZnSe nanobelts were studied. The observed electrostatic fields and charge accumulation were attributed to spontaneous polarization present in the wurtzite regions since the contributions from piezoelectric polarization were shown to be insignificant based on geometric phase analysis. The spontaneous polarization for the wurtzite ZnSe was calculated to be psp = -(0.0029±0.00013) C/m2, whereas a first principles' calculation gave psp = -0.0063 C/m2. The atomic arrangements and polarity continuity at the zincblende/wurtzite interface were determined through aberration-corrected high-angle annular-dark-field imaging, which revealed no polarity reversal across the interface. Overall, the successful outcomes of these studies confirmed the capability of off-axis electron holography to provide quantitative electrostatic information for nanostructured materials.
ContributorsLi, Luying (Author) / McCartney, Martha R. (Thesis advisor) / Smith, David J. (Thesis advisor) / Treacy, Michael J. (Committee member) / Shumway, John (Committee member) / Drucker, Jeffery (Committee member) / Arizona State University (Publisher)
Created2011
Description
Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250°C.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235°C.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage.
ContributorsSummers, Nicholas, M.S (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2010