Matching Items (5)
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- All Subjects: Semiconductors
- Creators: Alford, Terry
Description
Carrier lifetime is one of the few parameters which can give information about the low defect densities in today's semiconductors. In principle there is no lower limit to the defect density determined by lifetime measurements. No other technique can easily detect defect densities as low as 10-9 - 10-10 cm-3 in a simple, contactless room temperature measurement. However in practice, recombination lifetime τr measurements such as photoconductance decay (PCD) and surface photovoltage (SPV) that are widely used for characterization of bulk wafers face serious limitations when applied to thin epitaxial layers, where the layer thickness is smaller than the minority carrier diffusion length Ln. Other methods such as microwave photoconductance decay (µ-PCD), photoluminescence (PL), and frequency-dependent SPV, where the generated excess carriers are confined to the epitaxial layer width by using short excitation wavelengths, require complicated configuration and extensive surface passivation processes that make them time-consuming and not suitable for process screening purposes. Generation lifetime τg, typically measured with pulsed MOS capacitors (MOS-C) as test structures, has been shown to be an eminently suitable technique for characterization of thin epitaxial layers. It is for these reasons that the IC community, largely concerned with unipolar MOS devices, uses lifetime measurements as a "process cleanliness monitor." However when dealing with ultraclean epitaxial wafers, the classic MOS-C technique measures an effective generation lifetime τg eff which is dominated by the surface generation and hence cannot be used for screening impurity densities. I have developed a modified pulsed MOS technique for measuring generation lifetime in ultraclean thin p/p+ epitaxial layers which can be used to detect metallic impurities with densities as low as 10-10 cm-3. The widely used classic version has been shown to be unable to effectively detect such low impurity densities due to the domination of surface generation; whereas, the modified version can be used suitably as a metallic impurity density monitoring tool for such cases.
ContributorsElhami Khorasani, Arash (Author) / Alford, Terry (Thesis advisor) / Goryll, Michael (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2013
Description
The goal of this work is to develop low cost and highly efficient hybrid solar cells based on semiconductor nanoparticles (NPs). Hybrid solar cells have been demonstrated to take advantages of both inorganic and organic semiconductors by employing simple soluble process. In order to improve the power conversion efficiency (PCE), the bulk heterojunction (BHJ) of cadmium selenide (CdSe) tetrapods (TPs) and poly (3-hexylthiophene) (P3HT) are introduced as an electron acceptor and donor, respectively. The dimension of CdSe TPs and the 3D spatial distribution of CdSe TPs:P3HT photoactive blends are investigated to improve optical and electrical properties of photovoltaic devices. Hybrid solar cells having long-armed CdSe TPs and P3HT establish higher PCE of 1.12% when compared to device employing short-armed TPs of 0.80%. The device performance are improved by using longer armed CdSe TPs, which aids in better percolation connectivity and reduced charge hopping events, thus leading to better charge transport. The device architecture of hybrid solar cells is examined to assist vertical phase separation (VPS). Improvement of VPS in hybrid solar cells using CdSe TPs:P3HT photoactive blends is systematically manipulated by solution processed interfacial layers, resulting in enhanced device performance. Multi-layered hybrid solar cells assist better light absorption, efficient charge carrier transport, and increase of the surface contact area. In this work, hole transport assisting layer (HTAL)/BHJ photoactive layer (BPL)/electron transport assisting layer (ETAL) or HTAL/BPL/ETAL (HBE) multi-layered structure is introduced, similarly to p-type layer/intermixed photoactive layer
-type layer (p-i-n) structure of organic photovoltaic devices. To further control the improvement of the device performance, the effects of nano-scale morphology from solvents having different boiling points, the various shapes of semiconductor NPs, and the emergence of blending NPs are demonstrated. The formation of favorable 3D networks in photoactive layer is attributed to enhance the efficient charge transport by the optimized combination of semiconductor NPs in polymer matrix.
-type layer (p-i-n) structure of organic photovoltaic devices. To further control the improvement of the device performance, the effects of nano-scale morphology from solvents having different boiling points, the various shapes of semiconductor NPs, and the emergence of blending NPs are demonstrated. The formation of favorable 3D networks in photoactive layer is attributed to enhance the efficient charge transport by the optimized combination of semiconductor NPs in polymer matrix.
ContributorsLee, Kyu Sung (Author) / Jabbour, Ghassan E. (Thesis advisor) / Alford, Terry (Thesis advisor) / Krause, Stephen (Committee member) / Arizona State University (Publisher)
Created2012
Description
Global photovoltaic (PV) module installation in 2018 is estimated to exceed 100 GW, and crystalline Si (c-Si) solar cell-based modules have a share more than 90% of the global PV market. To reduce the social cost of PV electricity, further developments in reliability of solar panels are expected. These will lead to realize longer module lifetime and reduced levelized cost of energy. As many as 86 failure modes are observed in PV modules [1] and series resistance increase is one of the major durability issues of all. Series resistance constitutes emitter sheet resistance, metal-semiconductor contact resistance, and resistance across the metal-solder ribbon. Solder bond degradation at the cell interconnect is one of the primary causes for increase in series resistance, which is also considered to be an invisible defect [1]. Combination of intermetallic compounds (IMC) formation during soldering and their growth due to solid state diffusion over its lifetime result in formation of weak interfaces between the solar cell and the interconnect. Thermal cycling under regular operating conditions induce thermo-mechanical fatigue over these weak interfaces resulting in contact reduction or loss. Contact reduction or loss leads to increase in series resistance which further manifests into power and fill factor loss. The degree of intermixing of metallic interfaces and contact loss depends on climatic conditions as temperature and humidity (moisture ingression into the PV module laminate) play a vital role in reaction kinetics of these layers. Modules from Arizona and Florida served as a good sample set to analyze the effects of hot and humid climatic conditions respectively. The results obtained in the current thesis quantifies the thickness of IMC formation from SEM-EDS profiles, where similar modules obtained from different climatic conditions were compared. The results indicate the thickness of the IMC and detachment degree to be growing with age and operating temperatures of the module. This can be seen in CuxSny IMC which is thicker in the case of Arizona module. The results obtained from FL
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aged modules also show that humidity accelerates the formation of IMC as they showed thicker AgxSny layer and weak interconnect-contact interfaces as compared to Arizona modules. It is also shown that climatic conditions have different effects on rate at which CuxSny and AgxSny intermetallic compounds are formed.
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aged modules also show that humidity accelerates the formation of IMC as they showed thicker AgxSny layer and weak interconnect-contact interfaces as compared to Arizona modules. It is also shown that climatic conditions have different effects on rate at which CuxSny and AgxSny intermetallic compounds are formed.
ContributorsBuddha, Viswa Sai Pavan (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Alford, Terry (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Arizona State University (Publisher)
Created2018
Description
Diamond transistors are promising as high-power and high-frequency devices having higher efficiencies than conventional transistors. Diamond possesses superior electronic properties, such as a high bandgap (5.47 eV), high breakdown voltage (>10 MV cm−1 ), high electron and hole mobilities [4500 and 3800 cm2 V−1 · s−1, respectively], high electron and hole saturation velocities (1.5 × 107 and 1.05 × 107 cm s−1, respectively), and high thermal conductivity [22 W cm−1 · K−1], compared to conventional semiconductors. Reportedly, the diamond field-effect transistors (FETs) have shown transition frequencies (fT) of 45 and 70 GHz, maximum oscillation frequency (fmax) of 120 GHz, and radiofrequency (RF) power densities of 2.1 and 3.8 W mm−1 at 1 GHz. A two-dimensional-hole-gas (2DHG) surface channel forms on H-diamond by transfer doping from adsorbates/dielectrics in contact with H-diamond surface. However, prior studies indicate that charge transfer at the dielectric/ H-diamond interface could result in relatively low mobility attributed to interface scattering from the transferred negative charge to acceptor region. H-terminated diamond exhibits a negative electron affinity (NEA) of -1.1 to -1.3 eV, which is crucial to enable charge transfer doping. To overcome these limitations modulation doping, that is, selective doping, that leads to spatial separation of the MoO3 acceptor layer from the hole channel on H-diamond has been proposed. Molybdenum oxide (MoO3) was used as dielectric as it has electron affinity of 5.9eV and could align its conduction band minimum (CBM) below the valence band maximum (VBM) of H-terminated diamond. The band alignment provides the driving potential for charge transfer. Hafnium oxide (HfO2) was used as interfacial layer since it is a high-k oxide insulator (∼25), having large Eg (5.6 eV), high critical breakdown field, and high thermal stability. This study presents photoemission measurements of the electronic band alignments of the MoO3/HfO2/H-diamond layer structure to gain insight into the driving potential for the negative charge transfer and the location of the negative charges near the interface, in the HfO2 layer or in the MoO3 layer. The diamond hole concentration, mobility, and sheet resistance were characterized for MoO3/HfO2/H-Diamond with HfO2 layers of 0, 2 and 4 nm thickness.
ContributorsDeshmukh, Aditya Vilasrao (Author) / Nemanich, Robert J. (Thesis advisor) / Alford, Terry (Committee member) / Yang, Sui (Committee member) / Arizona State University (Publisher)
Created2024
Description
Wide bandgap semiconductors are of much current interest due to their superior electrical properties. This dissertation describes electron microscopy characterization of GaN-on-GaN structures for high-power vertical device applications. Unintentionally-doped (UID) GaN layers grown homoepitaxially via metal-organic chemical vapor deposition on freestanding GaN substrates, were subjected to dry etching, and layers of UID-GaN/p-GaN were over-grown. The as-grown and regrown heterostructures were examined in cross-section using transmission electron microscopy (TEM). Two different etching treatments, fast-etch-only and multiple etches with decreasing power, were employed. The fast-etch-only devices showed GaN-on-GaN interface at etched location, and low device breakdown voltages were measured (~ 45-95V). In comparison, no interfaces were visible after multiple etching steps, and the corresponding breakdown voltages were much higher (~1200-1270V). These results emphasized importance of optimizing surface etching techniques for avoiding degraded device performance.
The morphology of GaN-on-GaN devices after reverse-bias electrical stressing to breakdown was investigated. All failed devices had irreversible structural damage, showing large surface craters (~15-35 microns deep) with lengthy surface cracks. Cross-sectional TEM of failed devices showed high densities of threading dislocations (TDs) around the cracks and near crater surfaces. Progressive ion-milling across damaged devices revealed high densities of TDs and the presence of voids beneath cracks: these features were not observed in unstressed devices. The morphology of GaN substrates grown by hydride vapor-phase epitaxy (HVPE) and by ammonothermal methods were correlated with reverse-bias results. HVPE substrates showed arrays of surface features when observed by X-ray topography (XRT). All fabricated devices that overlapped with these features had typical reverse-bias voltages less than 100V at a leakage current limit of 10-6 A. In contrast, devices not overlapping with such features reached voltages greater than 300V. After etching, HVPE substrate surfaces showed defect clusters and macro-pits, whereas XRT images of ammonothermal substrate revealed no visible features. However, some devices fabricated on ammonothermal substrate failed at low voltages. Devices on HVPE and ammonothermal substrates with low breakdown voltages showed crater-like surface damage and revealed TDs (~25µm deep) and voids; such features were not observed in devices reaching higher voltages. These results should assist in developing protocols to fabricate reliable high-voltage devices.
ContributorsPeri, Prudhvi Ram (Author) / Smith, David J. (Thesis advisor) / Alford, Terry (Committee member) / Mccartney, Martha R (Committee member) / Nemanich, Robert (Committee member) / Zhao, Yuji (Committee member) / Arizona State University (Publisher)
Created2021