Matching Items (104)
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- Creators: Chakrabarti, Chaitali
- Creators: Ogras, Umit Y.
- All Subjects: Electrical Engineering
- Status: Published
Description
Visual navigation is a useful and important task for a variety of applications. As the prevalence of robots increase, there is an increasing need for energy-efficient navigation methods as well. Many aspects of efficient visual navigation algorithms have been implemented in the literature, but there is a lack of work on evaluation of the efficiency of the image sensors. In this thesis, two methods are evaluated: adaptive image sensor quantization for traditional camera pipelines as well as new event-based sensors for low-power computer vision.The first contribution in this thesis is an evaluation of performing varying levels of sensor linear and logarithmic quantization with the task of visual simultaneous localization and mapping (SLAM). This unconventional method can provide efficiency benefits with a trade off between accuracy of the task and energy-efficiency. A new sensor quantization method, gradient-based quantization, is introduced to improve the accuracy of the task. This method only lowers the bit level of parts of the image that are less likely to be important in the SLAM algorithm since lower bit levels signify better energy-efficiency, but worse task accuracy. The third contribution is an evaluation of the efficiency and accuracy of event-based camera intensity representations for the task of optical flow. The results of performing a learning based optical flow are provided for each of five different reconstruction methods along with ablation studies. Lastly, the challenges of an event feature-based SLAM system are presented with results demonstrating the necessity for high quality and high resolution event data. The work in this thesis provides studies useful for examining tradeoffs for an efficient visual navigation system with traditional and event vision sensors. The results of this thesis also provide multiple directions for future work.
ContributorsChristie, Olivia Catherine (Author) / Jayasuriya, Suren (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Yang, Yezhou (Committee member) / Arizona State University (Publisher)
Created2022
Description
Machine learning techniques have found extensive application in dynamic fields like drones, self-driving vehicles, surveillance, and more. Their effectiveness stems from meticulously crafted deep neural networks (DNNs), extensive data gathering efforts, and resource-intensive model training processes. However, due to the unpredictable nature of the environment, these systems will inevitably encounter input samples that deviate from the distribution of their original training data, resulting in instability and performance degradation.To effectively detect the emergence of out-of-distribution (OOD) data, this dissertation first proposes a novel, self-supervised approach that evaluates the Mahalanobis distance between the in-distribution (ID) and OOD in gradient space. A binary classifier is then introduced to guide the label selection for gradients calculation, which further boosts the detection performance.
Next, to continuously adapt the new OOD into the existing knowledge base, an unified framework for novelty detection and continual learning is proposed. The binary classifier, trained to distinguish OOD data from ID, is connected sequentially with the pre-trained model to form a “N + 1” classifier, where “N” represents prior knowledge which contains N classes and “1” refers to the newly arrival OOD. This continual learning process continues as “N+1+1+1+...”, assimilating the knowledge of each new OOD instance into the system.
Finally, this dissertation demonstrates the practical implementation of novelty detection and continual learning within the domain of thermal analysis. To rapidly address the impact of voids in thermal interface material (TIM), a continuous adaptation approach is proposed, which integrates trainable nodes into the graph at the locations where abnormal thermal behaviors are detected. With minimal training overhead, the model can quickly adapts to the change caused by the defects and regenerate accurate thermal prediction.
In summary, this dissertation proposes several algorithms and practical applications in continual learning aimed at enhancing the stability and adaptability of the system. All proposed algorithms are validated through extensive experiments conducted on benchmark datasets such as CIFAR-10, CIFAR-100, TinyImageNet for continual learning, and real thermal data for thermal analysis.
ContributorsSun, Jingbo (Author) / Cao, Yu (Thesis advisor) / Chhabria, Vidya (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Fan, Deliang (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2024
Description
Millimeter-wave (mmWave) and sub-terahertz (sub-THz) systems aim to utilize the large bandwidth available at these frequencies. This has the potential to enable several future applications that require high data rates, such as autonomous vehicles and digital twins. These systems, however, have several challenges that need to be addressed to realize their gains in practice. First, they need to deploy large antenna arrays and use narrow beams to guarantee sufficient receive power. Adjusting the narrow beams of the large antenna arrays incurs massive beam training overhead. Second, the sensitivity to blockages is a key challenge for mmWave and THz networks. Since these networks mainly rely on line-of-sight (LOS) links, sudden link blockages highly threaten the reliability of the networks. Further, when the LOS link is blocked, the network typically needs to hand off the user to another LOS basestation, which may incur critical time latency, especially if a search over a large codebook of narrow beams is needed. A promising way to tackle both these challenges lies in leveraging additional side information such as visual, LiDAR, radar, and position data. These sensors provide rich information about the wireless environment, which can be utilized for fast beam and blockage prediction. This dissertation presents a machine-learning framework for sensing-aided beam and blockage prediction. In particular, for beam prediction, this work proposes to utilize visual and positional data to predict the optimal beam indices. For the first time, this work investigates the sensing-aided beam prediction task in a real-world vehicle-to-infrastructure and drone communication scenario. Similarly, for blockage prediction, this dissertation proposes a multi-modal wireless communication solution that utilizes bimodal machine learning to perform proactive blockage prediction and user hand-off. Evaluations on both real-world and synthetic datasets illustrate the promising performance of the proposed solutions and highlight their potential for next-generation communication and sensing systems.
ContributorsCharan, Gouranga (Author) / Alkhateeb, Ahmed (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Turaga, Pavan (Committee member) / Michelusi, Nicolò (Committee member) / Arizona State University (Publisher)
Created2024
Description
Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations that can occur in the field lead to significant testing and validation challenges. For example, designers have to ensure that FHE devices continue to meet specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has to be part of the test procedures developed for FHE devices. This paper is the first to analyze stress experience at different parts of FHE devices under different bending conditions. Then develop a novel methodology to maximize the test coverage with minimum number of text vectors with the help of a mixed integer linear programming formulation.
ContributorsGao, Hang (Author) / Ozev, Sule (Thesis advisor) / Ogras, Umit Y. (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2018
Description
Medical ultrasound imaging is widely used today because of it being non-invasive and cost-effective. Flow estimation helps in accurate diagnosis of vascular diseases and adds an important dimension to medical ultrasound imaging. Traditionally flow estimation is done using Doppler-based methods which only estimate velocity in the beam direction. Thus when blood vessels are close to being orthogonal to the beam direction, there are large errors in the estimation results. In this dissertation, a low cost blood flow estimation method that does not have the angle dependency of Doppler-based methods, is presented.
First, a velocity estimator based on speckle tracking and synthetic lateral phase is proposed for clutter-free blood flow.
Speckle tracking is based on kernel matching and does not have any angle dependency. While velocity estimation in axial dimension is accurate, lateral velocity estimation is challenging due to reduced resolution and lack of phase information. This work presents a two tiered method which estimates the pixel level movement using sum-of-absolute difference, and then estimates the sub-pixel level using synthetic phase information in the lateral dimension. Such a method achieves highly accurate velocity estimation with reduced complexity compared to a cross correlation based method. The average bias of the proposed estimation method is less than 2% for plug flow and less than 7% for parabolic flow.
Blood is always accompanied by clutter which originates from vessel wall and surrounding tissues. As magnitude of the blood signal is usually 40-60 dB lower than magnitude of the clutter signal, clutter filtering is necessary before blood flow estimation. Clutter filters utilize the high magnitude and low frequency features of clutter signal to effectively remove them from the compound (blood + clutter) signal. Instead of low complexity FIR filter or high complexity SVD-based filters, here a power/subspace iteration based method is proposed for clutter filtering. Excellent clutter filtering performance is achieved for both slow and fast moving clutters with lower complexity compared to SVD-based filters. For instance, use of the proposed method results in the bias being less than 8% and standard deviation being less than 12% for fast moving clutter when the beam-to-flow-angle is $90^o$.
Third, a flow rate estimation method based on kernel power weighting is proposed. As the velocity estimator is a kernel-based method, the estimation accuracy degrades near the vessel boundary. In order to account for kernels that are not fully inside the vessel, fractional weights are given to these kernels based on their signal power. The proposed method achieves excellent flow rate estimation results with less than 8% bias for both slow and fast moving clutters.
The performance of the velocity estimator is also evaluated for challenging models. A 2D version of our two-tiered method is able to accurately estimate velocity vectors in a spinning disk as well as in a carotid bifurcation model, both of which are part of the synthetic aperture vector flow imaging (SA-VFI) challenge of 2018. In fact, the proposed method ranked 3rd in the challenge for testing dataset with carotid bifurcation. The flow estimation method is also evaluated for blood flow in vessels with stenosis. Simulation results show that the proposed method is able to estimate the flow rate with less than 9% bias.
First, a velocity estimator based on speckle tracking and synthetic lateral phase is proposed for clutter-free blood flow.
Speckle tracking is based on kernel matching and does not have any angle dependency. While velocity estimation in axial dimension is accurate, lateral velocity estimation is challenging due to reduced resolution and lack of phase information. This work presents a two tiered method which estimates the pixel level movement using sum-of-absolute difference, and then estimates the sub-pixel level using synthetic phase information in the lateral dimension. Such a method achieves highly accurate velocity estimation with reduced complexity compared to a cross correlation based method. The average bias of the proposed estimation method is less than 2% for plug flow and less than 7% for parabolic flow.
Blood is always accompanied by clutter which originates from vessel wall and surrounding tissues. As magnitude of the blood signal is usually 40-60 dB lower than magnitude of the clutter signal, clutter filtering is necessary before blood flow estimation. Clutter filters utilize the high magnitude and low frequency features of clutter signal to effectively remove them from the compound (blood + clutter) signal. Instead of low complexity FIR filter or high complexity SVD-based filters, here a power/subspace iteration based method is proposed for clutter filtering. Excellent clutter filtering performance is achieved for both slow and fast moving clutters with lower complexity compared to SVD-based filters. For instance, use of the proposed method results in the bias being less than 8% and standard deviation being less than 12% for fast moving clutter when the beam-to-flow-angle is $90^o$.
Third, a flow rate estimation method based on kernel power weighting is proposed. As the velocity estimator is a kernel-based method, the estimation accuracy degrades near the vessel boundary. In order to account for kernels that are not fully inside the vessel, fractional weights are given to these kernels based on their signal power. The proposed method achieves excellent flow rate estimation results with less than 8% bias for both slow and fast moving clutters.
The performance of the velocity estimator is also evaluated for challenging models. A 2D version of our two-tiered method is able to accurately estimate velocity vectors in a spinning disk as well as in a carotid bifurcation model, both of which are part of the synthetic aperture vector flow imaging (SA-VFI) challenge of 2018. In fact, the proposed method ranked 3rd in the challenge for testing dataset with carotid bifurcation. The flow estimation method is also evaluated for blood flow in vessels with stenosis. Simulation results show that the proposed method is able to estimate the flow rate with less than 9% bias.
ContributorsWei, Siyuan (Author) / Chakrabarti, Chaitali (Thesis advisor) / Papandreou-Suppappola, Antonia (Committee member) / Ogras, Umit Y. (Committee member) / Wenisch, Thomas F. (Committee member) / Arizona State University (Publisher)
Created2018
Description
This dissertation proposes and presents two different passive sigma-delta
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
ContributorsEROL, OSMAN EMIR (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ogras, Umit Y. (Committee member) / Blain-Christen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
As integrated technologies are scaling down, there is an increasing trend in the
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
ContributorsShafiee, Maryam (Author) / Ozev, Sule (Thesis advisor) / Diaz, Rodolfo (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2018
Description
Vision processing on traditional architectures is inefficient due to energy-expensive off-chip data movements. Many researchers advocate pushing processing close to the sensor to substantially reduce data movements. However, continuous near-sensor processing raises the sensor temperature, impairing the fidelity of imaging/vision tasks.
The work characterizes the thermal implications of using 3D stacked image sensors with near-sensor vision processing units. The characterization reveals that near-sensor processing reduces system power but degrades image quality. For reasonable image fidelity, the sensor temperature needs to stay below a threshold, situationally determined by application needs. Fortunately, the characterization also identifies opportunities -- unique to the needs of near-sensor processing -- to regulate temperature based on dynamic visual task requirements and rapidly increase capture quality on demand.
Based on the characterization, the work proposes and investigate two thermal management strategies -- stop-capture-go and seasonal migration -- for imaging-aware thermal management. The work present parameters that govern the policy decisions and explore the trade-offs between system power and policy overhead. The work's evaluation shows that the novel dynamic thermal management strategies can unlock the energy-efficiency potential of near-sensor processing with minimal performance impact, without compromising image fidelity.
The work characterizes the thermal implications of using 3D stacked image sensors with near-sensor vision processing units. The characterization reveals that near-sensor processing reduces system power but degrades image quality. For reasonable image fidelity, the sensor temperature needs to stay below a threshold, situationally determined by application needs. Fortunately, the characterization also identifies opportunities -- unique to the needs of near-sensor processing -- to regulate temperature based on dynamic visual task requirements and rapidly increase capture quality on demand.
Based on the characterization, the work proposes and investigate two thermal management strategies -- stop-capture-go and seasonal migration -- for imaging-aware thermal management. The work present parameters that govern the policy decisions and explore the trade-offs between system power and policy overhead. The work's evaluation shows that the novel dynamic thermal management strategies can unlock the energy-efficiency potential of near-sensor processing with minimal performance impact, without compromising image fidelity.
ContributorsKodukula, Venkatesh (Author) / LiKamWa, Robert (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Brunhaver, John (Committee member) / Arizona State University (Publisher)
Created2019
Description
The past decade has seen a tremendous surge in running machine learning (ML) functions on mobile devices, from mere novelty applications to now indispensable features for the next generation of devices.
While the mobile platform capabilities range widely, long battery life and reliability are common design concerns that are crucial to remain competitive.
Consequently, state-of-the-art mobile platforms have become highly heterogeneous by combining a powerful CPUs with GPUs to accelerate the computation of deep neural networks (DNNs), which are the most common structures to perform ML operations.
But traditional von Neumann architectures are not optimized for the high memory bandwidth and massively parallel computation demands required by DNNs.
Hence, propelling research into non-von Neumann architectures to support the demands of DNNs.
The re-imagining of computer architectures to perform efficient DNN computations requires focusing on the prohibitive demands presented by DNNs and alleviating them. The two central challenges for efficient computation are (1) large memory storage and movement due to weights of the DNN and (2) massively parallel multiplications to compute the DNN output.
Introducing sparsity into the DNNs, where certain percentage of either the weights or the outputs of the DNN are zero, greatly helps with both challenges. This along with algorithm-hardware co-design to compress the DNNs is demonstrated to provide efficient solutions to greatly reduce the power consumption of hardware that compute DNNs. Additionally, exploring emerging technologies such as non-volatile memories and 3-D stacking of silicon in conjunction with algorithm-hardware co-design architectures will pave the way for the next generation of mobile devices.
Towards the objectives stated above, our specific contributions include (a) an architecture based on resistive crosspoint array that can update all values stored and compute matrix vector multiplication in parallel within a single cycle, (b) a framework of training DNNs with a block-wise sparsity to drastically reduce memory storage and total number of computations required to compute the output of DNNs, (c) the exploration of hardware implementations of sparse DNNs and architectural guidelines to reduce power consumption for the implementations in monolithic 3D integrated circuits, and (d) a prototype chip in 65nm CMOS accelerator for long-short term memory networks trained with the proposed block-wise sparsity scheme.
While the mobile platform capabilities range widely, long battery life and reliability are common design concerns that are crucial to remain competitive.
Consequently, state-of-the-art mobile platforms have become highly heterogeneous by combining a powerful CPUs with GPUs to accelerate the computation of deep neural networks (DNNs), which are the most common structures to perform ML operations.
But traditional von Neumann architectures are not optimized for the high memory bandwidth and massively parallel computation demands required by DNNs.
Hence, propelling research into non-von Neumann architectures to support the demands of DNNs.
The re-imagining of computer architectures to perform efficient DNN computations requires focusing on the prohibitive demands presented by DNNs and alleviating them. The two central challenges for efficient computation are (1) large memory storage and movement due to weights of the DNN and (2) massively parallel multiplications to compute the DNN output.
Introducing sparsity into the DNNs, where certain percentage of either the weights or the outputs of the DNN are zero, greatly helps with both challenges. This along with algorithm-hardware co-design to compress the DNNs is demonstrated to provide efficient solutions to greatly reduce the power consumption of hardware that compute DNNs. Additionally, exploring emerging technologies such as non-volatile memories and 3-D stacking of silicon in conjunction with algorithm-hardware co-design architectures will pave the way for the next generation of mobile devices.
Towards the objectives stated above, our specific contributions include (a) an architecture based on resistive crosspoint array that can update all values stored and compute matrix vector multiplication in parallel within a single cycle, (b) a framework of training DNNs with a block-wise sparsity to drastically reduce memory storage and total number of computations required to compute the output of DNNs, (c) the exploration of hardware implementations of sparse DNNs and architectural guidelines to reduce power consumption for the implementations in monolithic 3D integrated circuits, and (d) a prototype chip in 65nm CMOS accelerator for long-short term memory networks trained with the proposed block-wise sparsity scheme.
ContributorsKadetotad, Deepak Vinayak (Author) / Seo, Jae-Sun (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Vrudhula, Sarma (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2019
Description
In recent years, conventional convolutional neural network (CNN) has achieved outstanding performance in image and speech processing applications. Unfortunately, the pooling operation in CNN ignores important spatial information which is an important attribute in many applications. The recently proposed capsule network retains spatial information and improves the capabilities of traditional CNN. It uses capsules to describe features in multiple dimensions and dynamic routing to increase the statistical stability of the network.
In this work, we first use capsule network for overlapping digit recognition problem. We evaluate the performance of the network with respect to recognition accuracy, convergence and training time per epoch. We show that capsule network achieves higher accuracy when training set size is small. When training set size is larger, capsule network and conventional CNN have comparable recognition accuracy. The training time per epoch for capsule network is longer than conventional CNN because of the dynamic routing algorithm. An analysis of the GPU timing shows that adjusting the capsule structure can help decrease the time complexity of the dynamic routing algorithm significantly.
Next, we design a capsule network for speech recognition, specifically, overlapping word recognition. We use both capsule network and conventional CNN to recognize 2 overlapping words in speech files created from 5 word classes. We show that capsule network achieves a considerably higher recognition accuracy (96.92%) compared to conventional CNN (85.19%). Our results show that capsule network recognizes overlapping word by recognizing each individual word in the speech. We also verify the scalability of capsule network by increasing the number of word classes from 5 to 10. Capsule network still shows a high recognition accuracy of 95.42% in case of 10 words while the accuracy of conventional CNN decreases sharply to 73.18%.
In this work, we first use capsule network for overlapping digit recognition problem. We evaluate the performance of the network with respect to recognition accuracy, convergence and training time per epoch. We show that capsule network achieves higher accuracy when training set size is small. When training set size is larger, capsule network and conventional CNN have comparable recognition accuracy. The training time per epoch for capsule network is longer than conventional CNN because of the dynamic routing algorithm. An analysis of the GPU timing shows that adjusting the capsule structure can help decrease the time complexity of the dynamic routing algorithm significantly.
Next, we design a capsule network for speech recognition, specifically, overlapping word recognition. We use both capsule network and conventional CNN to recognize 2 overlapping words in speech files created from 5 word classes. We show that capsule network achieves a considerably higher recognition accuracy (96.92%) compared to conventional CNN (85.19%). Our results show that capsule network recognizes overlapping word by recognizing each individual word in the speech. We also verify the scalability of capsule network by increasing the number of word classes from 5 to 10. Capsule network still shows a high recognition accuracy of 95.42% in case of 10 words while the accuracy of conventional CNN decreases sharply to 73.18%.
ContributorsXiong, Yan (Author) / Chakrabarti, Chaitali (Thesis advisor) / Berisha, Visar (Thesis advisor) / Weng, Yang (Committee member) / Arizona State University (Publisher)
Created2018