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Description
In the last few decades, extensive research efforts have been focused on scaling down silicon-based complementary metal-oxide semiconductor (CMOS) technology to enable the continuation of Moore’s law. State-of-art CMOS includes fully depleted silicon-on-insulator (FDSOI) field-effect-transistors (FETs) with ultra-thin silicon channels (6 nm), as well as other three-dimensional (3D) device architectures like Fin-FETs, nanosheet FETs, etc. Significant research efforts have characterized these technologies towards various applications, and at different conditions including a wide range of temperatures from room temperature (300 K) down to cryogenic temperatures. Theoretical efforts have studied ultrascaled devices using Landauer theory to further understand their transport properties and predict their performance in the quasi-ballistic regime.Further scaling of CMOS devices requires the introduction of new semiconducting channel materials, as now established by the research community. Here, two-dimensional (2D) semiconductors have emerged as a promising candidate to replace silicon for next-generation ultrascaled CMOS devices. These emerging 2D semiconductors also have applications beyond CMOS, for example in novel memory, neuromorphic, and spintronic devices. Graphene is a promising candidate for spintronic devices due to its outstanding spin transport properties as evidenced by numerous studies in non-local lateral spin valve (LSV) geometries. The essential components of graphene-based LSV, such as graphene FETs, metal-graphene contacts, and tunneling barriers, were individually investigated as part of this doctoral dissertation.
In this work, several contributions were made to these CMOS and beyond CMOS technologies. This includes comprehensive characterization and modeling of FDSOI nanoscale FETs from room temperature down to cryogenic temperatures. Using Landauer theory for nanoscale transistors, FDSOI devices were analyzed and modeled under quasi-ballistic operation. This was extended towards a virtual-source modeling approach that accounts for temperature-dependent quasi-ballistic transport and back-gate biasing effects. Additionally, graphene devices with ultrathin high-k gate dielectrics were investigated towards FETs, non-volatile memory, and spintronic devices. New contributions were made relating to charge trapping effects and their impact on graphene device electrostatics (Dirac voltage shifts) and transport properties (impact on mobility and conductivity). This work also studied contact resistance and tunneling effects using transfer length method (TLM) graphene FET structures and magnetic tunneling junction (MTJ) towards graphene-based LSV.
ContributorsZhou, Guantong (Author) / Sanchez Esqueda, Ivan (Thesis advisor) / Vasileska, Dragica (Committee member) / Tongay, Sefaattin (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2023
Description
The research of alternative materials and new device architectures to exceed the limits of conventional silicon-based devices has been sparked by the persistent pursuit of semiconductor technology scaling. The development of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2), well-known member of the transition metal dichalcogenide (TMD) family, has made great strides towards ultrascaled two-dimensional (2D) field-effect-transistors (FETs). The scaling issues facing silicon-based complementary metal-oxide-semiconductor (CMOS) technologies can be solved by 2D FETs, which show extraordinary potential.This dissertation provides a comprehensive experimental analysis relating to improvements in p-type metal-oxide-semiconductor (PMOS) FETs with few-layer WSe2 and high-κ metal gate (HKMG) stacks. Compared to this works improved methods, standard metallization (more damaging to underlying channel) results in significant Fermi-level pinning, although Schottky barrier heights remain small (< 100 meV) when using high work function metals. Temperature-dependent analysis reveals a dominant contribution to contact resistance from the damaged channel access region. Thus, through less damaging metallization methods combined with strongly scaled HKMG stacks significant improvements were achieved in contact resistance and PMOS FET overall performance. A clean contact/channel interface was achieved through high-vacuum evaporation and temperature-controlled stepped deposition. Theoretical analysis using a Landauer transport adapted to WSe2 Schottky barrier FETs (SB-FETs) elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance towards the ultimate CMOS scaling limit.
Next, this dissertation discusses how device electrical characteristics are affected by scaling of equivalent oxide thickness (EOT) and by adopting double-gate FET architectures, as well as how this might support CMOS scaling. An improved gate control over the channel is made possible by scaling EOT, improving on-off current ratios, carrier mobility, and subthreshold swing. This study also elucidates the impact of EOT scaling on FET gate hysteresis attributed to charge-trapping effects in high-κ-dielectrics prepared by atomic layer deposition (ALD). These developments in 2D FETs offer a compelling alternative to conventional silicon-based devices and a path for continued transistor scaling. This research contributes to ongoing efforts in 2D materials for future semiconductor technologies. Finally, this work introduces devices based on emerging Janus TMDs and bismuth oxyselenide (Bi2O2Se) layered semiconductors.
ContributorsPatoary, Md Naim Hossain (Author) / Sanchez Esqueda, Ivan (Thesis advisor) / Tongay, Sefaattin (Committee member) / Vasileska, Dragica (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2023
Description
Realization of efficient, high-bandgap photovoltaic cells produced using economically viable methods is a technological advance that could change the way we generate and use energy, and thereby accelerate the development of human civilization. There is a need to engineer a semiconductor material for solar cells, particularly multijunction cells, that has high (1.6-2.0 eV) bandgap, has relatively inactive defects, is thermodynamically stable under normal operating conditions with the potential for cost-effective thin-film growth in mass production.This work focuses on a material system made of gallium, indium, and phosphorus – the ternary semiconductor GaInP. GaInP based photovoltaic cells in single-crystal form have demonstrated excellent power conversion efficiency, however, growth of single-crystal GaInP is prohibitively expensive. While growth of polycrystalline GaInP is expected to lower production costs, polycrystalline GaInP is also expected to have a high density of electronically active defects, about which little is reported in scientific literature. This work presents the first study of synthesis, and structural and optoelectronic characterization of polycrystalline GaInP thin films.
In addition, this work models the best performance of polycrystalline solar cells achievable with a given grain size with grain-boundary/surface recombination velocity as a variable parameter. The effects of defect characteristics at the surface and layer properties such as doping and thickness on interface recombination velocity are also modeled.
Recombination velocities at the free surface of single-crystal GaInP and after deposition of various dielectric layers on GaInP are determined experimentally using time-resolved photoluminescence decay measurements. In addition, experimental values of bulk lifetime and surface recombination velocity in well-passivated single crystal AlInP-GaInP based double heterostructures are also measured for comparison to polycrystalline material systems.
A novel passivation method – aluminum-assisted post-deposition treatment or Al-PDT – was developed which shows promise as a general passivation and material improvement technique for polycrystalline thin films. In the GaInP system, this aluminum post-deposition treatment has demonstrated improvement in the minority carrier lifetime to 44 ns at 80 K. During development of the passivation process, aluminum diffusivity in GaInP was measured using TEM-EDS line scans. Introduction, development, and refinement of this novel passivation mechanism in polycrystalline GaInP could initiate the development of a new family of passivation treatments, potentially improving the optoelectronic response of other polycrystalline compound semiconductors as well.
ContributorsChikhalkar, Abhinav (Author) / King, Richard R (Thesis advisor) / Honsberg, Christiana (Committee member) / Newman, Nathan (Committee member) / Tongay, Sefaattin (Committee member) / Arizona State University (Publisher)
Created2021