Matching Items (16)
Filtering by
- All Subjects: Electrical Engineering
- Genre: Doctoral Dissertation
Description
The first part describes Metal Semiconductor Field Effect Transistor (MESFET) based fundamental analog building blocks designed and fabricated in a single poly, 3-layer metal digital CMOS technology utilizing fully depletion mode MESFET devices. DC characteristics were measured by varying the power supply from 2.5V to 5.5V. The measured DC transfer curves of amplifiers show good agreement with the simulated ones with extracted models from the same process. The accuracy of the current mirror showing inverse operation is within ±15% for the current from 0 to 1.5mA with the power supply from 2.5 to 5.5V. The second part presents a low-power image recognition system with a novel MESFET device fabricated on a CMOS substrate. An analog image recognition system with power consumption of 2.4mW/cell and a response time of 6µs is designed, fabricated and characterized. The experimental results verified the accuracy of the extracted SPICE model of SOS MESFETs. The response times of 4µs and 6µs for one by four and one by eight arrays, respectively, are achieved with the line recognition. Each core cell for both arrays consumes only 2.4mW. The last part presents a CMOS low-power transceiver in MICS band is presented. The LNA core has an integrated mixer in a folded configuration. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. The SRO is used in a wakeup RX for the wake-up signal reception. The all digital frequency-locked loop drives a class AB power amplifier in a transmitter. The sensitivity of -85dBm in the wakeup RX is achieved with the power consumption of 320µW and 400µW at the data rates of 100kb/s and 200kb/s from 1.8V, respectively. The sensitivities of -70dBm and -98dBm in the data-link RX are achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600µW and 1.5mW at 1.2V and 1.8V, respectively.
ContributorsKim, Sung (Author) / Bakkaloglu, Bertan (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Cao, Yu (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2011
Description
Sliding-Mode Control (SMC) has several benefits over traditional Proportional-Integral-Differential (PID) control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. An All-Digital Sliding-Mode (ADSM) controlled DC-DC converter, utilizing single-bit oversampled frequency domain digitizers is proposed. In the proposed approach, feedback and reference digitizing Analog-to-Digital Converters (ADC) are based on a single-bit, first order Sigma-Delta frequency to digital converter, running at 32MHz over-sampling rate. The ADSM regulator achieves 1% settling time in less than 5uSec for a load variation of 600mA. The sliding-mode controller utilizes a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady state error (or DC offset), and limits the switching frequency range, which are the two common problems associated with sliding-mode controllers. The IC is designed and fabricated on a 0.35um CMOS process occupying an active area of 2.72mm-squared. Measured peak efficiency is 83%.
ContributorsDashtestani, Ahmad (Author) / Bakkaloglu, Bertan (Thesis advisor) / Thornton, Trevor (Committee member) / Song, Hongjiang (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.
ContributorsGhajar, Mohammad Reza (Author) / Thornton, Trevor (Thesis advisor) / Aberle, James T., 1961- (Committee member) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2012
Description
This thesis presents a gas sensor readout IC for amperometric and conductometric electrochemical sensors. The Analog Front-End (AFE) readout circuit enables tracking long term exposure to hazardous gas fumes in diesel and gasoline equipments, which may be correlated to diseases. Thus, the detection and discrimination of gases using microelectronic gas sensor system is required. This thesis describes the research, development, implementation and test of a small and portable based prototype platform for chemical gas sensors to enable a low-power and low noise gas detection system. The AFE reads out the outputs of eight conductometric sensor array and eight amperometric sensor arrays. The IC consists of a low noise potentiostat, and associated 9bit current-steering DAC for sensor stimulus, followed by the first order nested chopped £U£G ADC. The conductometric sensor uses a current driven approach for extracting conductance of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage to the sensors and an I/V converter to measure current out of the sensor. The core area for the AFE is 2.65x0.95 mm2. The proposed system achieves 91 dB SNR at 1.32 mW quiescent power consumption per channel. With digital offset storage and nested chopping, the readout chain achieves 500 fÝV input referred offset.
ContributorsKim, Hyun-Tae (Author) / Bakkaloglu, Bertan (Thesis advisor) / Vermeire, Bert (Committee member) / Spanias, Andreas (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2011
Description
Graphene, a one atomic thick planar sheet of carbon atoms, has a zero gap band structure with a linear dispersion relation. This unique property makes graphene a favorite for physicists and engineers, who are trying to understand the mechanism of charge transport in graphene and using it as channel material for field effect transistor (FET) beyond silicon. Therefore, an in-depth exploring of these electrical properties of graphene is urgent, which is the purpose of this dissertation. In this dissertation, the charge transport and quantum capacitance of graphene were studied. Firstly, the transport properties of back-gated graphene transistor covering by high dielectric medium were systematically studied. The gate efficiency increased by up to two orders of magnitude in the presence of a high top dielectric medium, but the mobility did not change significantly. The results strongly suggested that the previously reported top dielectric medium-induced charge transport properties of graphene FETs were possibly due to the increase of gate capacitance, rather than enhancement of carrier mobility. Secondly, a direct measurement of quantum capacitance of graphene was performed. The quantum capacitance displayed a non-zero minimum at the Dirac point and a linear increase on both sides of the minimum with relatively small slopes. The findings - which were not predicted by theory for ideal graphene - suggested that scattering from charged impurities also influences the quantum capacitance. The capacitances in aqueous solutions at different ionic concentrations were also measured, which strongly suggested that the longstanding puzzle about the interfacial capacitance in carbon-based electrodes had a quantum origin. Finally, the transport and quantum capacitance of epitaxial graphene were studied simultaneously, the quantum capacitance of epitaxial graphene was extracted, which was similar to that of exfoliated graphene near the Dirac Point, but exhibited a large sub-linear behavior at high carrier density. The self-consistent theory was found to provide a reasonable description of the transport data of the epitaxial graphene device, but a more complete theory was needed to explain both the transport and quantum capacitance data.
ContributorsXia, Jilin (Author) / Tao, N.J. (Thesis advisor) / Ferry, David (Committee member) / Thornton, Trevor (Committee member) / Tsui, Raymond (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2010
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
In the last few decades, extensive research efforts have been focused on scaling down silicon-based complementary metal-oxide semiconductor (CMOS) technology to enable the continuation of Moore’s law. State-of-art CMOS includes fully depleted silicon-on-insulator (FDSOI) field-effect-transistors (FETs) with ultra-thin silicon channels (6 nm), as well as other three-dimensional (3D) device architectures like Fin-FETs, nanosheet FETs, etc. Significant research efforts have characterized these technologies towards various applications, and at different conditions including a wide range of temperatures from room temperature (300 K) down to cryogenic temperatures. Theoretical efforts have studied ultrascaled devices using Landauer theory to further understand their transport properties and predict their performance in the quasi-ballistic regime.Further scaling of CMOS devices requires the introduction of new semiconducting channel materials, as now established by the research community. Here, two-dimensional (2D) semiconductors have emerged as a promising candidate to replace silicon for next-generation ultrascaled CMOS devices. These emerging 2D semiconductors also have applications beyond CMOS, for example in novel memory, neuromorphic, and spintronic devices. Graphene is a promising candidate for spintronic devices due to its outstanding spin transport properties as evidenced by numerous studies in non-local lateral spin valve (LSV) geometries. The essential components of graphene-based LSV, such as graphene FETs, metal-graphene contacts, and tunneling barriers, were individually investigated as part of this doctoral dissertation.
In this work, several contributions were made to these CMOS and beyond CMOS technologies. This includes comprehensive characterization and modeling of FDSOI nanoscale FETs from room temperature down to cryogenic temperatures. Using Landauer theory for nanoscale transistors, FDSOI devices were analyzed and modeled under quasi-ballistic operation. This was extended towards a virtual-source modeling approach that accounts for temperature-dependent quasi-ballistic transport and back-gate biasing effects. Additionally, graphene devices with ultrathin high-k gate dielectrics were investigated towards FETs, non-volatile memory, and spintronic devices. New contributions were made relating to charge trapping effects and their impact on graphene device electrostatics (Dirac voltage shifts) and transport properties (impact on mobility and conductivity). This work also studied contact resistance and tunneling effects using transfer length method (TLM) graphene FET structures and magnetic tunneling junction (MTJ) towards graphene-based LSV.
ContributorsZhou, Guantong (Author) / Sanchez Esqueda, Ivan (Thesis advisor) / Vasileska, Dragica (Committee member) / Tongay, Sefaattin (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2023
Description
Over the past few years, research into the use of doped diamond in electronics has seen an exponential growth. In the course of finding ways to reduce the contact resistivity, nanocarbon materials have been an interesting focus. In this work, the transfer length method (TLM) was used to investigate Ohmic contact properties using the tri-layer stack Ti/Pt/Au on nitrogen-doped n-type conducting nano-carbon (nanoC) layers grown on (100) diamond substrates. The nanocarbon material was characterized using Secondary Ion Mass Spectrometry (SIMS), Scanning electron Microscopy (SEM) X-ray diffraction (XRD), Raman scattering and Hall effect measurements to probe the materials characteristics. Room temperature electrical measurements were taken, and samples were annealed to observe changes in electrical conductivity. Low specific contact resistivity values of 8 x 10^-5 Ωcm^2 were achieved, which was almost two orders of magnitude lower than previously reported values. The results were attributed to the increased nitrogen incorporation, and the presence of electrically active defects which leads to an increase in conduction in the nanocarbon. Further a study of light phosphorus doped layers using similar methods with Ti/Pt/Au contacts again yielded a low contact resistivity of about 9.88 x 10^-2 Ωcm^2 which is an interesting prospect among lightly doped diamond films for applications in devices such as transistors. In addition, for the first time, hafnium was substituted for Ti in the contact stack (Hf/Pt/Au) and studied on nitrogen doped nanocarbon films, which resulted in low contact resistivity values on the order of 10^-2 Ωcm^2. The implications of the results were discussed, and recommendations for improving the experimental process was outlined. Lastly, a method for the selective area growth of nanocarbon was developed and studied and the results provided an insight into how different characterizations can be used to confirm the presence of the nanocrystalline diamond material, the limitations due to the film thickness was explored and ideas for future work was proposed.
ContributorsAmonoo, Evangeline Abena (Author) / Thornton, Trevor (Thesis advisor) / Alford, Terry L (Thesis advisor) / Anwar, Shahriar (Committee member) / Theodore, David (Committee member) / Arizona State University (Publisher)
Created2023
Description
Wide Bandgap (WBG) semiconductor materials are shaping day-to-day technologyby introducing powerful and more energy responsible devices. These materials have
opened the door for building basic semiconductor devices which are superior in terms of
handling high voltages, high currents, power, and temperature which is not possible using
conventional silicon technology. As the research continues in the field of WBG based
devices, there is a potential chance that the power electronics industry can save billions of
dollars deploying energy-efficient circuits in high power conversion electronics. Diamond,
silicon carbide and gallium nitride are the top three contenders among which diamond can
significantly outmatch others in a variety of properties. However, diamond technology is
still in its early phase of development and there are challenges involved in many aspects of
processing a successful integrated circuit. The work done in this research addresses three
major aspects of problems related to diamond technology. In the first part, the applicability
of compact modeling and Technology Computer-Aided Design (TCAD) modeling
technique for diamond Schottky p-i-n diodes has been demonstrated. The compact model
accurately predicts AC, DC and nonlinear behavior of the diode required for fast circuit
simulation. Secondly, achieving low resistance ohmic contact onto n-type diamond is one
of the major issues that is still an open research problem as it determines the performance
of high-power RF circuits and switching losses in power converters circuits. So, another
portion of this thesis demonstrates the achievement of very low resistance ohmic contact
(~ 10-4 Ω⋅cm2) onto n-type diamond using nano crystalline carbon interface layer. Using
the developed TCAD and compact models for low resistance contacts, circuit level
predictions show improvements in RF performance. Lastly, an initial study of breakdown
characteristics of diamond and cubic boron nitride heterostructure is presented. This study
serves as a first step for making future transistors using diamond and cubic boron nitride –
a very less explored material system in literature yet promising for extreme circuit
applications involving high power and temperature.
ContributorsJHA, VISHAL (Author) / Thornton, Trevor (Thesis advisor) / Goodnick, Stephen (Committee member) / Nemanich, Robert (Committee member) / Alford, Terry (Committee member) / Hoque, Mazhar (Committee member) / Arizona State University (Publisher)
Created2023
Description
An efficient thermal solver is available in the CMC that allows modeling self-heating in the electrical simulations, which treats phonons as flux and solves the energy balance equation to quantify thermal effects. Using this solver, thermal simulations were performed on GaN-HEMTs in order to test effect of gate architectures on the DC and RF performance of the device. A Π- gate geometry is found to suppress 19.75% more hot electrons corresponding to a DC power of 2.493 W/mm for Vgs = -0.6V (max transconductance) with respect to the initial T-gate. For the DC performance, the output current, Ids is nearly same for each device configuration over the entire bias range. For the RF performance, the current gain was evaluated over a frequency range 20 GHz to 120 GHz in each device for both thermal (including self-heating) and isothermal (without self-heating). The evaluated cutoff frequency is around 7% lower for the thermal case than the isothermal case. The simulated cutoff frequency closely follows the experimental cutoff frequency. The work was extended to the study of ultra-wide bandgap material (Diamond), where isotope effect causes major deterioration in thermal conductivity. In this case, bulk phonons are modeled as semiclassical particles solving the nonlinear Peierls - Boltzmann transport equation with a stochastic approach. Simulations were performed for 0.001% (ultra-pure), 0.1% and 1.07% isotope concentration (13C) of diamond, showing good agreement with the experimental values. Further investigation was performed on the effect of isotope on the dynamics of individual phonon branches, thermal conductivity and the mean free path, to identify the dominant phonon branch. Acoustic phonons are found to be the principal contributors to thermal conductivity across all isotope concentrations with transverse acoustic (TA2) branch is the dominant branch with a contribution of 40% at room temperature and 37% at 500K. Mean free path computations show the lower bound of device dimensions in order to obtain maximum thermal conductivity. At 300K, the lowest mean free path (which is attributed to Longitudinal Optical phonon) reduces from 24nm to 8 nm for isotope concentration of 0.001% and 1.07% respectively. Similarly, the maximum mean free path (which is attributed to Longitudinal Acoustic phonon) reduces from 4 µm to 3.1 µm, respectively, for the same isotope concentrations. Furthermore, PETSc (Portable, Extensible Toolkit for Scientific Computation) developed by Argonne National Lab, was included in the existing Cellular Monte Carlo device simulator as a Poisson solver to further extend the capability of the simulator. The validity of the solver was tested performing 2D and 3D simulations and the results were compared with the well-established multigrid Poisson solver.
ContributorsAcharjee, Joy (Author) / Saraniti, Marco (Thesis advisor) / Goodnick, Stephen (Committee member) / Thornton, Trevor (Committee member) / Wang, Robert (Committee member) / Arizona State University (Publisher)
Created2024