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- All Subjects: Electrical Engineering
- Creators: Ogras, Umit Y.
Description
Flow measurement has always been one of the most critical processes in many industrial and clinical applications. The dynamic behavior of flow helps to define the state of a process. An industrial example would be that in an aircraft, where the rate of airflow passing the aircraft is used to determine the speed of the plane. A clinical example would be that the flow of a patient's breath which could help determine the state of the patient's lungs. This project is focused on the flow-meter that are used for airflow measurement in human lungs. In order to do these measurements, resistive-type flow-meters are commonly used in respiratory measurement systems. This method consists of passing the respiratory flow through a fluid resistive component, while measuring the resulting pressure drop, which is linearly related to volumetric flow rate. These types of flow-meters typically have a low frequency response but are adequate for most applications, including spirometry and respiration monitoring. In the case of lung parameter estimation methods, such as the Quick Obstruction Method, it becomes important to have a higher frequency response in the flow-meter so that the high frequency components in the flow are measurable. The following three types of flow-meters were: a. Capillary type b. Screen Pneumotach type c. Square Edge orifice type To measure the frequency response, a sinusoidal flow is generated with a small speaker and passed through the flow-meter that is connected to a large, rigid container. True flow is proportional to the derivative of the pressure inside the container. True flow is then compared with the measured flow, which is proportional to the pressure drop across the flow-meter. In order to do the characterization, two LabVIEW data acquisition programs have been developed, one for transducer calibration, and another one that records flow and pressure data for frequency response testing of the flow-meter. In addition, a model that explains the behavior exhibited by the flow-meter has been proposed and simulated. This model contains a fluid resistor and inductor in series. The final step in this project was to approximate the frequency response data to the developed model expressed as a transfer function.
ContributorsHu, Jianchen (Author) / Macia, Narciso (Thesis advisor) / Pollat, Scott (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2013
Description
Photovoltaic (PV) module nameplates typically provide the module's electrical characteristics at standard test conditions (STC). The STC conditions are: irradiance of 1000 W/m2, cell temperature of 25oC and sunlight spectrum at air mass 1.5. However, modules in the field experience a wide range of environmental conditions which affect their electrical characteristics and render the nameplate data insufficient in determining a module's overall, actual field performance. To make sound technical and financial decisions, designers and investors need additional performance data to determine the energy produced by modules operating under various field conditions. The angle of incidence (AOI) of sunlight on PV modules is one of the major parameters which dictate the amount of light reaching the solar cells. The experiment was carried out at the Arizona State University- Photovoltaic Reliability Laboratory (ASU-PRL). The data obtained was processed in accordance with the IEC 61853-2 model to obtain relative optical response of the modules (response which does not include the cosine effect). The results were then compared with theoretical models for air-glass interface and also with the empirical model developed by Sandia National Laboratories. The results showed that all modules with glass as the superstrate had identical optical response and were in agreement with both the IEC 61853-2 model and other theoretical and empirical models. The performance degradation of module over years of exposure in the field is dependent upon factors such as environmental conditions, system configuration, etc. Analyzing the degradation of power and other related performance parameters over time will provide vital information regarding possible degradation rates and mechanisms of the modules. An extensive study was conducted by previous ASU-PRL students on approximately 1700 modules which have over 13 years of hot- dry climatic field condition. An analysis of the results obtained in previous ASU-PRL studies show that the major degradation in crystalline silicon modules having glass/polymer construction is encapsulant discoloration (causing short circuit current drop) and solder bond degradation (causing fill factor drop due to series resistance increase). The power degradation for crystalline silicon modules having glass/glass construction was primarily attributed to encapsulant delamination (causing open-circuit voltage drop).
ContributorsVasantha Janakeeraman, Suryanarayana (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Macia, Narciso (Committee member) / Arizona State University (Publisher)
Created2013
Description
This is a two-part thesis: Part 1 of this thesis tests and validates the methodology and mathematical models of the International Electrotechnical Commission (IEC) 61853-2 standard for the measurement of angle of incidence (AOI) effects on photovoltaic modules. Flat-plate photovoltaic modules in the field operate under a wide range of environmental conditions. The purpose of IEC 61853-2 is to characterize photovoltaic modules' performance under specific environmental conditions. Part 1 of this report focuses specifically on AOI. To accurately test and validate IEC 61853-2 standard for measuring AOI, meticulous experimental setup and test procedures were followed. Modules of five different photovoltaic technology types with glass superstrates were tested. Test results show practically identical relative light transmission plots for all five test modules. The experimental results were compared to theoretical and empirical models for relative light transmission of air-glass interface. IEC 61853-2 states "for the flat glass superstrate modules, the AOI test does not need to be performed; rather, the data of a flat glass air interface can be used." The results obtained in this thesis validate this statement. This work was performed in collaboration with another Master of Science student (Surynarayana Janakeeraman) and the test results are presented in two masters theses. Part 2 of this thesis is to develop non-intrusive techniques to accurately measure the quantum efficiency (QE) of a single-junction crystalline silicon cell within a commercial module. This thesis will describe in detail all the equipment and conditions necessary to measure QE and discuss the factors which may influence this measurement. The ability to utilize a non-intrusive test to measure quantum efficiency of a cell within a module is extremely beneficial for reliability testing of commercial modules. Detailed methodologies for this innovative test procedure are not widely available in industry because equipment and measurement techniques have not been explored extensively. This paper will provide a literature review describing relevant theories and measurement techniques related to measuring the QE of a cell within a module. The testing methodology and necessary equipment will be described in detail. Results and conclusions provide the overall accuracy of the measurements and discuss the parameters affecting these measurements.
ContributorsKnisely, Brett (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Macia, Narciso (Committee member) / Arizona State University (Publisher)
Created2013
Description
ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed.
ContributorsKumar, Sushil (Author) / Clark, Lawrence (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Switch mode DC/DC converters are suited for battery powered applications, due to their high efficiency, which help in conserving the battery lifetime. Fixed Frequency PWM based converters, which are generally used for these applications offer good voltage regulation, low ripple and excellent efficiency at high load currents. However at light load currents, fixed frequency PWM converters suffer from poor efficiencies The PFM control offers higher efficiency at light loads at the cost of a higher ripple. The PWM has a poor efficiency at light loads but good voltage ripple characteristics, due to a high switching frequency. To get the best of both control modes, both loops are used together with the control switched from one loop to another based on the load current. Such architectures are referred to as hybrid converters. While transition from PFM to PWM loop can be made by estimating the average load current, transition from PFM to PWM requires voltage or peak current sensing. This theses implements a hysteretic PFM solution for a synchronous buck converter with external MOSFET's, to achieve efficiencies of about 80% at light loads. As the PFM loop operates independently of the PWM loop, a transition circuit for automatically transitioning from PFM to PWM is implemented. The transition circuit is implemented digitally without needing any external voltage or current sensing circuit.
ContributorsVivek, Parasuram (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ogras, Umit Y. (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2014
Description
Photovoltaic (PV) modules appear to have three classifications of failure: Infant mortality, normal-life failure, and end-of-life failure. Little is known of the end-of-life failures experienced by PV modules due to their inherent longevity. Accelerated Life Testing (ALT) has been at the crux of this lifespan prediction; however, without naturally failing modules an accurate acceleration factor cannot be determined for use in ALT. By observing modules that have been aged in the field, a comparison can be made with modules undergoing accelerated testing. In this study an investigation on about 1900 aged (10-17 years) grid-tied PV modules installed in the desert climatic condition of Arizona was undertaken. The investigation was comprised of a check sheet that documented any visual defects and their severity, infrared (IR) scanning, and current-voltage (I-V) curve measurements. After data was collected on modules, an analysis was performed to classify the failure modes and to determine the annual performance degradation rates.
ContributorsSuleske, Adam Alfred (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Macia, Narciso (Committee member) / Arizona State University (Publisher)
Created2010
Description
Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations that can occur in the field lead to significant testing and validation challenges. For example, designers have to ensure that FHE devices continue to meet specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has to be part of the test procedures developed for FHE devices. This paper is the first to analyze stress experience at different parts of FHE devices under different bending conditions. Then develop a novel methodology to maximize the test coverage with minimum number of text vectors with the help of a mixed integer linear programming formulation.
ContributorsGao, Hang (Author) / Ozev, Sule (Thesis advisor) / Ogras, Umit Y. (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2018
Description
Medical ultrasound imaging is widely used today because of it being non-invasive and cost-effective. Flow estimation helps in accurate diagnosis of vascular diseases and adds an important dimension to medical ultrasound imaging. Traditionally flow estimation is done using Doppler-based methods which only estimate velocity in the beam direction. Thus when blood vessels are close to being orthogonal to the beam direction, there are large errors in the estimation results. In this dissertation, a low cost blood flow estimation method that does not have the angle dependency of Doppler-based methods, is presented.
First, a velocity estimator based on speckle tracking and synthetic lateral phase is proposed for clutter-free blood flow.
Speckle tracking is based on kernel matching and does not have any angle dependency. While velocity estimation in axial dimension is accurate, lateral velocity estimation is challenging due to reduced resolution and lack of phase information. This work presents a two tiered method which estimates the pixel level movement using sum-of-absolute difference, and then estimates the sub-pixel level using synthetic phase information in the lateral dimension. Such a method achieves highly accurate velocity estimation with reduced complexity compared to a cross correlation based method. The average bias of the proposed estimation method is less than 2% for plug flow and less than 7% for parabolic flow.
Blood is always accompanied by clutter which originates from vessel wall and surrounding tissues. As magnitude of the blood signal is usually 40-60 dB lower than magnitude of the clutter signal, clutter filtering is necessary before blood flow estimation. Clutter filters utilize the high magnitude and low frequency features of clutter signal to effectively remove them from the compound (blood + clutter) signal. Instead of low complexity FIR filter or high complexity SVD-based filters, here a power/subspace iteration based method is proposed for clutter filtering. Excellent clutter filtering performance is achieved for both slow and fast moving clutters with lower complexity compared to SVD-based filters. For instance, use of the proposed method results in the bias being less than 8% and standard deviation being less than 12% for fast moving clutter when the beam-to-flow-angle is $90^o$.
Third, a flow rate estimation method based on kernel power weighting is proposed. As the velocity estimator is a kernel-based method, the estimation accuracy degrades near the vessel boundary. In order to account for kernels that are not fully inside the vessel, fractional weights are given to these kernels based on their signal power. The proposed method achieves excellent flow rate estimation results with less than 8% bias for both slow and fast moving clutters.
The performance of the velocity estimator is also evaluated for challenging models. A 2D version of our two-tiered method is able to accurately estimate velocity vectors in a spinning disk as well as in a carotid bifurcation model, both of which are part of the synthetic aperture vector flow imaging (SA-VFI) challenge of 2018. In fact, the proposed method ranked 3rd in the challenge for testing dataset with carotid bifurcation. The flow estimation method is also evaluated for blood flow in vessels with stenosis. Simulation results show that the proposed method is able to estimate the flow rate with less than 9% bias.
First, a velocity estimator based on speckle tracking and synthetic lateral phase is proposed for clutter-free blood flow.
Speckle tracking is based on kernel matching and does not have any angle dependency. While velocity estimation in axial dimension is accurate, lateral velocity estimation is challenging due to reduced resolution and lack of phase information. This work presents a two tiered method which estimates the pixel level movement using sum-of-absolute difference, and then estimates the sub-pixel level using synthetic phase information in the lateral dimension. Such a method achieves highly accurate velocity estimation with reduced complexity compared to a cross correlation based method. The average bias of the proposed estimation method is less than 2% for plug flow and less than 7% for parabolic flow.
Blood is always accompanied by clutter which originates from vessel wall and surrounding tissues. As magnitude of the blood signal is usually 40-60 dB lower than magnitude of the clutter signal, clutter filtering is necessary before blood flow estimation. Clutter filters utilize the high magnitude and low frequency features of clutter signal to effectively remove them from the compound (blood + clutter) signal. Instead of low complexity FIR filter or high complexity SVD-based filters, here a power/subspace iteration based method is proposed for clutter filtering. Excellent clutter filtering performance is achieved for both slow and fast moving clutters with lower complexity compared to SVD-based filters. For instance, use of the proposed method results in the bias being less than 8% and standard deviation being less than 12% for fast moving clutter when the beam-to-flow-angle is $90^o$.
Third, a flow rate estimation method based on kernel power weighting is proposed. As the velocity estimator is a kernel-based method, the estimation accuracy degrades near the vessel boundary. In order to account for kernels that are not fully inside the vessel, fractional weights are given to these kernels based on their signal power. The proposed method achieves excellent flow rate estimation results with less than 8% bias for both slow and fast moving clutters.
The performance of the velocity estimator is also evaluated for challenging models. A 2D version of our two-tiered method is able to accurately estimate velocity vectors in a spinning disk as well as in a carotid bifurcation model, both of which are part of the synthetic aperture vector flow imaging (SA-VFI) challenge of 2018. In fact, the proposed method ranked 3rd in the challenge for testing dataset with carotid bifurcation. The flow estimation method is also evaluated for blood flow in vessels with stenosis. Simulation results show that the proposed method is able to estimate the flow rate with less than 9% bias.
ContributorsWei, Siyuan (Author) / Chakrabarti, Chaitali (Thesis advisor) / Papandreou-Suppappola, Antonia (Committee member) / Ogras, Umit Y. (Committee member) / Wenisch, Thomas F. (Committee member) / Arizona State University (Publisher)
Created2018
Description
This dissertation proposes and presents two different passive sigma-delta
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
ContributorsEROL, OSMAN EMIR (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ogras, Umit Y. (Committee member) / Blain-Christen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
As integrated technologies are scaling down, there is an increasing trend in the
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
ContributorsShafiee, Maryam (Author) / Ozev, Sule (Thesis advisor) / Diaz, Rodolfo (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2018