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- All Subjects: Electrical Engineering
- Creators: Vasileska, Dragica
- Creators: Karady, George G.
- Creators: Cao, Yu
Description
Solar energy, including solar heating, solar architecture, solar thermal electricity and solar photovoltaics, is one of the primary energy sources replacing fossil fuels. Being one of the most important techniques, significant research has been conducted in solar cell efficiency improvement. Simulation of various structures and materials of solar cells provides a deeper understanding of device operation and ways to improve their efficiency. Over the last two decades, polycrystalline thin-film Cadmium-Sulfide and Cadmium-Telluride (CdS/CdTe) solar cells fabricated on glass substrates have been considered as one of the most promising candidate in the photovoltaic technologies, for their similar efficiency and low costs when compared to traditional silicon-based solar cells. In this work a fast one dimensional time-dependent/steady-state drift-diffusion simulator, accelerated by adaptive non-uniform mesh and automatic time-step control, for modeling solar cells has been developed and has been used to simulate a CdS/CdTe solar cell. These models are used to reproduce transients of carrier transport in response to step-function signals of different bias and varied light intensity. The time-step control models are also used to help convergence in steady-state simulations where constrained material constants, such as carrier lifetimes in the order of nanosecond and carrier mobility in the order of 100 cm2/Vs, must be applied.
ContributorsGuo, Da (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen M (Committee member) / Sankin, Igor (Committee member) / Arizona State University (Publisher)
Created2013
Description
An embedded HVDC system is a dc link with at least two ends being physically connected within a single synchronous ac network. The thesis reviews previous works on embedded HVDC, proposes a dynamic embedded HVDC model by PSCAD program, and compares the transient stability performance among AC, DC and embedded HVDC. The test results indicate that by installing the embedded HVDC, AC network transient stability performance has been largely improved. Therefore the thesis designs a novel frequency control topology for embedded HVDC. According to the dynamic performance test results, when the embedded HVDC system equipped with a frequency control, the system transient stability will be improved further.
ContributorsYu, Jicheng (Author) / Karady, George G. (Thesis advisor) / Hui, Yu (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis addresses the issue of making an economic case for energy storage in power systems. Bulk energy storage has often been suggested for large scale electric power systems in order to levelize load; store energy when it is inexpensive and discharge energy when it is expensive; potentially defer transmission and generation expansion; and provide for generation reserve margins. As renewable energy resource penetration increases, the uncertainty and variability of wind and solar may be alleviated by bulk energy storage technologies. The quadratic programming function in MATLAB is used to simulate an economic dispatch that includes energy storage. A program is created that utilizes quadratic programming to analyze various cases using a 2010 summer peak load from the Arizona transmission system, part of the Western Electricity Coordinating Council (WECC). The MATLAB program is used first to test the Arizona test bed with a low level of energy storage to study how the storage power limit effects several optimization out-puts such as the system wide operating costs. Very high levels of energy storage are then added to see how high level energy storage affects peak shaving, load factor, and other system applications. Finally, various constraint relaxations are made to analyze why the applications tested eventually approach a constant value. This research illustrates the use of energy storage which helps minimize the system wide generator operating cost by "shaving" energy off of the peak demand.
ContributorsRuggiero, John (Author) / Heydt, Gerald T (Thesis advisor) / Datta, Rajib (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2013
Description
ABSTRACT Developing new non-traditional device models is gaining popularity as the silicon-based electrical device approaches its limitation when it scales down. Membrane systems, also called P systems, are a new class of biological computation model inspired by the way cells process chemical signals. Spiking Neural P systems (SNP systems), a certain kind of membrane systems, is inspired by the way the neurons in brain interact using electrical spikes. Compared to the traditional Boolean logic, SNP systems not only perform similar functions but also provide a more promising solution for reliable computation. Two basic neuron types, Low Pass (LP) neurons and High Pass (HP) neurons, are introduced. These two basic types of neurons are capable to build an arbitrary SNP neuron. This leads to the conclusion that these two basic neuron types are Turing complete since SNP systems has been proved Turing complete. These two basic types of neurons are further used as the elements to construct general-purpose arithmetic circuits, such as adder, subtractor and comparator. In this thesis, erroneous behaviors of neurons are discussed. Transmission error (spike loss) is proved to be equivalent to threshold error, which makes threshold error discussion more universal. To improve the reliability, a new structure called motif is proposed. Compared to Triple Modular Redundancy improvement, motif design presents its efficiency and effectiveness in both single neuron and arithmetic circuit analysis. DRAM-based CMOS circuits are used to implement the two basic types of neurons. Functionality of basic type neurons is proved using the SPICE simulations. The motif improved adder and the comparator, as compared to conventional Boolean logic design, are much more reliable with lower leakage, and smaller silicon area. This leads to the conclusion that SNP system could provide a more promising solution for reliable computation than the conventional Boolean logic.
ContributorsAn, Pei (Author) / Cao, Yu (Thesis advisor) / Barnaby, Hugh (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2013
Description
Underground cables have been widely used in big cities. This is because underground cables offer the benefits of reducing visual impact and the disturbance caused by bad weather (wind, ice, snow, and the lightning strikes). Additionally, when placing power lines underground, the maintenance costs can also be reduced as a result. The underground cable rating calculation is the most critical part of designing the cable construction and cable installation. In this thesis, three contributions regarding the cable ampacity study have been made. First, an analytical method for rating of underground cables has been presented. Second, this research also develops the steady state and transient ratings for Salt River Project (SRP) 69 kV underground system using the commercial software CYMCAP for several typical substations. Third, to find an alternative way to predict the cable ratings, three regression models have been built. The residual plot and mean square error for the three methods have been analyzed. The conclusion is dawn that the nonlinear regression model provides the sufficient accuracy of the cable rating prediction for SRP's typical installation.
ContributorsWang, Tong (Author) / Tylavsky, Daniel (Thesis advisor) / Karady, George G. (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis concerns the flashover issue of the substation insulators operating in a polluted environment. The outdoor insulation equipment used in the power delivery infrastructure encounter different types of pollutants due to varied environmental conditions. Various methods have been developed by manufacturers and researchers to mitigate the flashover problem. The application of Room Temperature Vulcanized (RTV) silicone rubber is one such favorable method as it can be applied over the already installed units. Field experience has already showed that the RTV silicone rubber coated insulators have a lower flashover probability than the uncoated insulators. The scope of this research is to quantify the improvement in the flashover performance. Artificial contamination tests were carried on station post insulators for assessing their performance. A factorial experiment design was used to model the flashover performance. The formulation included the severity of contamination and leakage distance of the insulator samples. Regression analysis was used to develop a mathematical model from the data obtained from the experiments. The main conclusion drawn from the study is that the RTV coated insulators withstood much higher levels of contamination even when the coating had lost its hydrophobicity. This improvement in flashover performance was found to be in the range of 20-40%. A much better flashover performance was observed when the coating recovered its hydrophobicity. It was also seen that the adhesion of coating was excellent even after many tests which involved substantial discharge activity.
ContributorsGholap, Vipul (Author) / Gorur, Ravi S (Thesis advisor) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2013
Description
GaN high electron mobility transistors (HEMTs) based on the III-V nitride material system have been under extensive investigation because of their superb performance as high power RF devices. Two dimensional electron gas(2-DEG) with charge density ten times higher than that of GaAs-based HEMT and mobility much higher than Si enables a low on-resistance required for RF devices. Self-heating issues with GaN HEMT and lack of understanding of various phenomena are hindering their widespread commercial development. There is a need to understand device operation by developing a model which could be used to optimize electrical and thermal characteristics of GaN HEMT design for high power and high frequency operation. In this thesis work a physical simulation model of AlGaN/GaN HEMT is developed using commercially available software ATLAS from SILVACO Int. based on the energy balance/hydrodynamic carrier transport equations. The model is calibrated against experimental data. Transfer and output characteristics are the key focus in the analysis along with saturation drain current. The resultant IV curves showed a close correspondence with experimental results. Various combinations of electron mobility, velocity saturation, momentum and energy relaxation times and gate work functions were attempted to improve IV curve correlation. Thermal effects were also investigated to get a better understanding on the role of self-heating effects on the electrical characteristics of GaN HEMTs. The temperature profiles across the device were observed. Hot spots were found along the channel in the gate-drain spacing. These preliminary results indicate that the thermal effects do have an impact on the electrical device characteristics at large biases even though the amount of self-heating is underestimated with respect to thermal particle-based simulations that solve the energy balance equations for acoustic and optical phonons as well (thus take proper account of the formation of the hot-spot). The decrease in drain current is due to decrease in saturation carrier velocity. The necessity of including hydrodynamic/energy balance transport models for accurate simulations is demonstrated. Possible ways for improving model accuracy are discussed in conjunction with future research.
ContributorsChowdhury, Towhid (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Since its inception about three decades ago, silicon on insulator (SOI) technology has come a long way to be included in the microelectronics roadmap. Earlier, scientists and engineers focused on ways to increase the microprocessor clock frequency and speed. Today, with smart phones and tablets gaining popularity, power consumption has become a major factor. In this thesis, self-heating effects in a 25nm fully depleted (FD) SOI device are studied by implementing a 2-D particle based device simulator coupled self-consistently with the energy balance equations for both acoustic and optical phonons. Semi-analytical expressions for acoustic and optical phonon scattering rates (all modes) are derived and evaluated using quadratic dispersion relationships. Moreover, probability distribution functions for the final polar angle after scattering is also computed and the rejection technique is implemented for its selection. Since the temperature profile varies throughout the device, temperature dependent scattering tables are used for the electron transport kernel. The phonon energy balance equations are also modified to account for inelasticity in acoustic phonon scattering for all branches. Results obtained from this simulation help in understanding self-heating and the effects it has on the device characteristics. The temperature profiles in the device show a decreasing trend which can be attributed to the inelastic interaction between the electrons and the acoustic phonons. This is further proven by comparing the temperature plots with the simulation results that assume the elastic and equipartition approximation for acoustic and the Einstein model for optical phonons. Thus, acoustic phonon inelasticity and the quadratic phonon dispersion relationships play a crucial role in studying self-heating effects.
ContributorsGada, Manan Laxmichand (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David K. (Committee member) / Goodnick, Stephen M (Committee member) / Arizona State University (Publisher)
Created2013
Description
With the rapid growth of power systems and the concomitant technological advancements, the goal of achieving smart grids is no longer a vision but a foreseeable reality. Hence, the existing grids are undergoing infrastructural modifications to achieve the diverse characteristics of a smart grid. While there are many subjects associated with the operation of smart grids, this dissertation addresses two important aspects of smart grids: increased penetration of renewable resources, and increased reliance on sensor systems to improve reliability and performance of critical power system components. Present renewable portfolio standards are changing both structural and performance characteristics of power systems by replacing conventional generation with alternate energy resources such as photovoltaic (PV) systems. The present study investigates the impact of increased penetration of PV systems on steady state performance as well as transient stability of a large power system which is a portion of the Western U.S. interconnection. Utility scale and residential rooftop PVs are added to replace a portion of conventional generation resources. While steady state voltages are observed under various PV penetration levels, the impact of reduced inertia on transient stability performance is also examined. The simulation results obtained effectively identify both detrimental and beneficial impacts of increased PV penetration both for steady state stability and transient stability performance. With increased penetration of the renewable energy resources, and with the current loading scenario, more transmission system components such as transformers and circuit breakers are subject to increased stress and overloading. This research work explores the feasibility of increasing system reliability by applying condition monitoring systems to selected circuit breakers and transformers. A very important feature of smart grid technology is that this philosophy decreases maintenance costs by deploying condition monitoring systems that inform the operator of impending failures; or the approach can ameliorate problematic conditions. A method to identify the most critical transformers and circuit breakers with the aid of contingency ranking methods is presented in this study. The work reported in this dissertation parallels an industry sponsored study in which a considerable level of industry input and industry reported concerns are reflected.
ContributorsEftekharnejad, Sara (Author) / Heydt, Gerald (Thesis advisor) / Vittal, Vijay (Thesis advisor) / Si, Jennie (Committee member) / Tylavsky, Daniel (Committee member) / Arizona State University (Publisher)
Created2012
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 90nm nodes with less than a 5% error. Voltage-controlled delay lines at 65nm and 90nm are emulated by 32nm PANDA, which successfully match important analog metrics. And at-speed emulation is achieved as well. Several other 90nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H)
ContributorsXu, Cheng (Author) / Cao, Yu (Thesis advisor) / Blain Christen, Jennifer (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2012