Matching Items (28)
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- All Subjects: Electrical Engineering
- All Subjects: Audio amplifiers--Design and construction.
- Genre: Masters Thesis
- Creators: Barnaby, Hugh
Description
With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This thesis discusses one such block, the sub-ADC (Flash ADC), of the pipeline and sharing it with more than two of the parallel processing channels thereby reducing area and power and input load capacitance to each stage. This work presents a design of 'sub-ADC shared in a time-interleaved pipeline ADC' in the IBM 8HP process. It has been implemented with an offset-compensated, kickback-compensated, fast decision making (large input bandwidth) and low power comparator that forms the core part of the design.
ContributorsBikkina, Phaneendra Kumar (Author) / Barnaby, Hugh (Thesis advisor) / Mikkola, Esko (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
Description
The thesis focuses on cost-efficient integration of the electro-chemical residue sensor (ECRS), a novel sensor developed for the in situ and real-time measurement of the residual impurities left on the wafer surface and in the fine structures of patterned wafers during typical rinse processes, and wireless transponder circuitry that is based on RFID technology. The proposed technology uses only the NMOS FD-SOI transistors with amorphous silicon as active material with silicon nitride as a gate dielectric. The proposed transistor was simulated under the SILVACO ATLAS Simulation Framework. A parametric study was performed to study the impact of different gate lengths (6 μm to 56 μm), electron motilities (0.1 cm2/Vs to 1 cm2/Vs), gate dielectric (SiO2 and SiNx) and active materials (a-Si and poly-Si) specifications. Level-1 models, that are accurate enough to acquire insight into the circuit behavior and perform preliminary design, were successfully constructed by analyzing drain current and gate to node capacitance characteristics against drain to source and gate to source voltages. Using the model corresponding to SiNx as gate dielectric, a-Si:H as active material with electron mobility equal to 0.4 cm2/V-sec, an operational amplifier was designed and was tested in unity gain configuration at modest load-frequency specifications.
ContributorsPandit, Vedhas (Author) / Vermeire, Bert (Thesis advisor) / Barnaby, Hugh (Committee member) / Chae, Junseok (Committee member) / Arizona State University (Publisher)
Created2010
Description
The RADiation sensitive Field Effect Transistor (RADFET) has been conventionally used to measure radiation dose levels. These dose sensors are calibrated in such a way that a shift in threshold voltage, due to a build-up of oxide-trapped charge, can be used to estimate the radiation dose. In order to estimate the radiation dose level using RADFET, a wired readout circuit is necessary. Using the same principle of oxide-trapped charge build-up, but by monitoring the change in capacitance instead of threshold voltage, a wireless dose sensor can be developed. This RADiation sensitive CAPacitor (RADCAP) mounted on a resonant patch antenna can then become a wireless dose sensor. From the resonant frequency, the capacitance can be extracted which can be mapped back to estimate the radiation dose level. The capacitor acts as both radiation dose sensor and resonator element in the passive antenna loop. Since the MOS capacitor is used in passive state, characterizing various parameters that affect the radiation sensitivity is essential. Oxide processing technique, choice of insulator material, and thickness of the insulator, critically affect the dose response of the sensor. A thicker oxide improves the radiation sensitivity but reduces the dynamic range of dose levels for which the sensor can be used. The oxide processing scheme primarily determines the interface trap charge and oxide-trapped charge development; controlling this parameter is critical to building a better dose sensor.
ContributorsSrinivasan Gopalan, Madusudanan (Author) / Barnaby, Hugh (Thesis advisor) / Holbert, Keith E. (Committee member) / Yu, Hongyu (Committee member) / Arizona State University (Publisher)
Created2010
Description
Proton beam therapy has been proven to be effective for cancer treatment. Protons allow for complete energy deposition to occur inside patients, rendering this a superior treatment compared to other types of radiotherapy based on photons or electrons. This same characteristic makes quality assurance critical driving the need for detectors capable of direct beam positioning and fluence measurement. This work showcases a flexible and scalable data acquisition system for a multi-channel and segmented readout parallel plate ionization chamber instrument for proton beam fluence and positioning detection. Utilizing readily available, modern, off-the-shelf hardware components, including an FPGA with an embedded CPU in the same package, a data acquisition system for the detector was designed. The undemanding detector signal bandwidth allows the absence of ASICs and their associated costs and lead times in the system. The data acquisition system is showcased experimentally for a 96-readout channel detector demonstrating sub millisecond beam characteristics and beam reconstruction. The system demonstrated scalability up to 1064-readout channels, the limiting factor being FPGA I/O availability as well as amplification and sampling power consumption.
ContributorsAcuna Briceno, Rafael Andres (Author) / Barnaby, Hugh (Thesis advisor) / Brunhaver, John (Committee member) / Blyth, David (Committee member) / Arizona State University (Publisher)
Created2021
Description
Bipolar commercial-off-the-shelf (COTS) circuits are increasingly used in spacemissions due to the low cost per part. In space environments these devices are exposed to
ionizing radiation that degrades their performance. Testing to evaluate the performance of
these devices is a costly and lengthy process. As such methods that can help predict a
COTS part’s performance help alleviate these downsides. A modeling software for
predicting total ionizing dose (TID), enhanced low dose rate sensitivity (ELDRS), and
hydrogen gas on bipolar parts is introduced and expanded upon. The model is then
developed in several key ways that expand it’s features and usability in this field. A
physics based methodology of simulating interface traps (NIT) to expand the previously
experimental only database is detailed. This new methodology is also compared to
experimental data and used to establish a link between hydrogen concentration in the
oxide and packaged hydrogen gas. Links are established between Technology Computer
Aided Design (TCAD), circuit simulation, and experimental data. These links are then
used to establish a better foundation for the model. New methodologies are added to the
modeling software so that it is possible to simulate transient based characteristics like
slew rate.
ContributorsRoark, Samuel (Author) / Barnaby, Hugh (Thesis advisor) / Sanchez Esqueda, Ivan (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2022
Description
Most hardware today is based on von Neumann architecture separating memory from logic. Valuable processing time is lost in shuttling information back and forth between the two units, a problem called von Neumann bottleneck. As transistors are scaled further down, this bottleneck will make it harder to deliver performance in computing power. Adding to this is the increasing complexity of artificial intelligence logic. Thus, there is a need for a faster and more efficient method of computing. Neuromorphic systems deliver this by emulating the massively parallel and fault-tolerant computing capabilities of the human brain where the action potential is triggered by multiple inputs at once (spatial) or an input that builds up over time (temporal). Highly scalable memristors are key in these systems- they can maintain their internal resistive state based on previous current/voltage values thus mimicking the way the strength of two synapses in the brain can vary. The brain-inspired algorithms are implemented by vector matrix multiplications (VMMs) to provide neuronal outputs. High-density conductive bridging random access memory (CBRAM) crossbar arrays (CBAs) can perform VMMs parallelly with ultra-low energy.This research explores a simple planarization technique that could be potentially extended to integrate front-end-of-line (FEOL) processing of complementary metal oxide semiconductor (CMOS) circuitry with back-end-of-line (BEOL) processing of CBRAM CBAs for one-transistor one-resistor (1T1R) Neuromorphic CMOS chips where the transistor is part of the CMOS circuitry and the CBRAM forms the resistor. It is a photoresist (PR) and spin-on glass (SOG) based planarization recipe to planarize CBRAM electrode patterns on a silicon substrate. In this research, however, the planarization is only applied to mechanical grade (MG) silicon wafers without any CMOS layers on them. The planarization achieved was of a very high order (few tens of nanometers). Additionally, the recipe is cost-effective, provides good quality films and simple as only two types of process technologies are involved- lithography and dry etching.
Subsequent processing would involve depositing the CBRAM layers onto the planarized electrodes to form the resistor. Finally, the entire process flow is to be replicated onto wafers with CMOS layers to form the 1T1R circuit.
ContributorsBiswas, Prabaha (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Velo, Yago Gonzalez (Committee member) / Arizona State University (Publisher)
Created2021
Description
ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR and hence the maximum resolution that can be achieved by ADC. With the RSD algorithm and the range overlap, the sub ADC can tolerate large comparator offsets leaving the linearity and accuracy requirement for the DAC and residue gain stage. Typically, the multiplying DAC requires high gain wide bandwidth op-amp and the design of this high gain op-amp becomes challenging in the deep submicron technologies. This work presents `A 12 bit 25MSPS 1.2V pipelined ADC using split CLS technique' in IBM 130nm 8HP process using only CMOS devices for the application of Large Hadron Collider (LHC). CLS technique relaxes the gain requirement of op-amp and improves the signal-to-noise ratio without increase in power or input sampling capacitor with rail-to-rail swing. An op-amp sharing technique has been incorporated with split CLS technique which decreases the number of op-amps and hence the power further. Entire pipelined converter has been implemented as six 2.5 bit RSD stages and hence decreases the latency associated with the pipelined architecture - one of the main requirements for LHC along with the power requirement. Two different OTAs have been designed to use in the split-CLS technique. Bootstrap switches and pass gate switches are used in the circuit along with a low power dynamic kick-back compensated comparator.
ContributorsSwaminathan, Visu Vaithiyanathan (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
Machine learning advancements have led to increasingly complex algorithms, resulting in significant energy consumption due to heightened memory-transfer requirements and inefficient vector matrix multiplication (VMM). To address this issue, many have proposed ReRAM analog in-memory computing (AIMC) as a solution. AIMC enhances the time-energy efficiency of VMM operations beyond conventional VMM digital hardware, such as a tensor processing unit (TPU), while substantially reducing memory-transfer demands through in-memory computing. As AIMC gains prominence as a solution, it becomes crucial to optimize ReRAM and analog crossbar architecture characteristics. This thesis introduces an application-specific integrated circuit (ASIC) tailored forcharacterizing ReRAM within a crossbar array architecture and discusses the interfacing techniques employed. It discusses ReRAM forming and programming techniques and showcases chip’s ability to utilize the write-verify programming method to write image pixels on a conductance heat map. Additionally, this thesis assesses the ASIC’s capability to characterize different aspects of ReRAM, including drift and noise characteristics. The research employs the chip to extract ReRAM data and models it within a crossbar array simulator, enabling its application in the classification of the CIFAR-10 dataset.
ContributorsShort, Jesse (Author) / Marinella, Matthew (Thesis advisor) / Barnaby, Hugh (Committee member) / Sanchez Esqueda, Ivan (Committee member) / Arizona State University (Publisher)
Created2023