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Description
One of the challenges in future semiconductor device design is excessive rise of power dissipation and device temperatures. With the introduction of new geometrically confined device structures like SOI, FinFET, nanowires and continuous incorporation of new materials with poor thermal conductivities in the device active region, the device thermal problem is expected to become more challenging in coming years. This work examines the degradation in the ON-current due to self-heating effects in 10 nm channel length silicon nanowire transistors. As part of this dissertation, a 3D electrothermal device simulator is developed that self-consistently solves electron Boltzmann transport equation with 3D energy balance equations for both the acoustic and the optical phonons. This device simulator predicts temperature variations and other physical and electrical parameters across the device for different bias and boundary conditions. The simulation results show insignificant current degradation for nanowire self-heating because of pronounced velocity overshoot effect. In addition, this work explores the role of various placement of the source and drain contacts on the magnitude of self-heating effect in nanowire transistors. This work also investigates the simultaneous influence of self-heating and random charge effects on the magnitude of the ON current for both positively and negatively charged single charges. This research suggests that the self-heating effects affect the ON-current in two ways: (1) by lowering the barrier at the source end of the channel, thus allowing more carriers to go through, and (2) via the screening effect of the Coulomb potential. To examine the effect of temperature dependent thermal conductivity of thin silicon films in nanowire transistors, Selberherr's thermal conductivity model is used in the device simulator. The simulations results show larger current degradation because of self-heating due to decreased thermal conductivity . Crystallographic direction dependent thermal conductivity is also included in the device simulations. Larger degradation is observed in the current along the [100] direction when compared to the [110] direction which is in agreement with the values for the thermal conductivity tensor provided by Zlatan Aksamija.
ContributorsHossain, Arif (Author) / Vasileska, Dragica (Thesis advisor) / Ahmed, Shaikh (Committee member) / Bakkaloglu, Bertan (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT An Ensemble Monte Carlo (EMC) computer code has been developed to simulate, semi-classically, spin-dependent electron transport in quasi two-dimensional (2D) III-V semiconductors. The code accounts for both three-dimensional (3D) and quasi-2D transport, utilizing either 3D or 2D scattering mechanisms, as appropriate. Phonon, alloy, interface roughness, and impurity scattering mechanisms are included, accounting for the Pauli Exclusion Principle via a rejection algorithm. The 2D carrier states are calculated via a self-consistent 1D Schrödinger-3D-Poisson solution in which the charge distribution of the 2D carriers in the quantization direction is taken as the spatial distribution of the squared envelope functions within the Hartree approximation. The wavefunctions, subband energies, and 2D scattering rates are updated periodically by solving a series of 1D Schrödinger wave equations (SWE) over the real-space domain of the device at fixed time intervals. The electrostatic potential is updated by periodically solving the 3D Poisson equation. Spin-polarized transport is modeled via a spin density-matrix formalism that accounts for D'yakanov-Perel (DP) scattering. Also, the code allows for the easy inclusion of additional scattering mechanisms and structural modifications to devices. As an application of the simulator, the current voltage characteristics of an InGaAs/InAlAs HEMT are simulated, corresponding to nanoscale III-V HEMTs currently being fabricated by Intel Corporation. The comparative effects of various scattering parameters, material properties and structural attributes are investigated and compared with experiments where reasonable agreement is obtained. The spatial evolution of spin-polarized carriers in prototypical Spin Field Effect Transistor (SpinFET) devices is then simulated. Studies of the spin coherence times in quasi-2D structures is first investigated and compared to experimental results. It is found that the simulated spin coherence times for GaAs structures are in reasonable agreement with experiment. The SpinFET structure studied is a scaled-down version of the InGaAs/InAlAs HEMT discussed in this work, in which spin-polarized carriers are injected at the source, and the coherence length is studied as a function of gate voltage via the Rashba effect.
ContributorsTierney, Brian David (Author) / Goodnick, Stephen (Thesis advisor) / Ferry, David (Committee member) / Akis, Richard (Committee member) / Saraniti, Marco (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
Description
Thermal effects in nano-scaled devices were reviewed and modeling methodologies to deal with this issue were discussed. The phonon energy balance equations model, being one of the important previous works regarding the modeling of heating effects in nano-scale devices, was derived. Then, detailed description was given on the Monte Carlo (MC) solution of the phonon Boltzmann Transport Equation. The phonon MC solver was developed next as part of this thesis. Simulation results of the thermal conductivity in bulk Si show good agreement with theoretical/experimental values from literature.
ContributorsYoo, Seung Kyung (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2015
Description
Thin-film modules of all technologies often suffer from performance degradation over time. Some of the performance changes are reversible and some are not, which makes deployment, testing, and energy-yield prediction more challenging. The most commonly alleged causes of instability in CdTe device, such as “migration of Cu,” have been investigated rigorously over the past fifteen years. As all defects, intrinsic or extrinsic, interact with the electrical potential and free carriers so that charged defects may drift in the electric field and changing ionization state with excess free carriers. Such complexity of interactions in CdTe makes understanding of temporal changes in device performance even more challenging. The goal of the work in this dissertation is, thus, to eliminate the ambiguity between the observed performance changes under stress and their physical root cause by enabling a depth of modeling that takes account of diffusion and drift at the atomistic level coupled to the electronic subsystem responsible for a PV device’s function. The 1D Unified Solver, developed as part of this effort, enables us to analyze PV devices at a greater depth.
In this dissertation, the implementation of a drift-diffusion model defect migration simulator, development of an implicit reaction scheme for total mass conservation, and a couple of other numerical schemes to improve the overall flexibility and robustness of this coupled Unified Solver is discussed. Preliminary results on Cu (with or without Cl-treatment) annealing simulations in both single-crystal CdTe wafer and poly-crystalline CdTe devices show promising agreement to experimental findings, providing a new perspective in the research of improving doping concentration hence the open-circuit voltage of CdTe technology. Furthermore, on the reliability side, in agreement of previous experimental reports, simulation results suggest possibility of Cu depletion in short-circuited cells stressed at elevated temperature. The developed solver also successfully demonstrated that mobile donor migration can be used to explain solar cell performance changes under different stress conditions.
In this dissertation, the implementation of a drift-diffusion model defect migration simulator, development of an implicit reaction scheme for total mass conservation, and a couple of other numerical schemes to improve the overall flexibility and robustness of this coupled Unified Solver is discussed. Preliminary results on Cu (with or without Cl-treatment) annealing simulations in both single-crystal CdTe wafer and poly-crystalline CdTe devices show promising agreement to experimental findings, providing a new perspective in the research of improving doping concentration hence the open-circuit voltage of CdTe technology. Furthermore, on the reliability side, in agreement of previous experimental reports, simulation results suggest possibility of Cu depletion in short-circuited cells stressed at elevated temperature. The developed solver also successfully demonstrated that mobile donor migration can be used to explain solar cell performance changes under different stress conditions.
ContributorsGuo, Da (Author) / Vasileska, Dragica (Thesis advisor) / Sankin, Igor (Committee member) / Goodnick, Stephen (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2017
Description
Semiconductor nanowires have the potential to emerge as the building blocks of next generation field-effect transistors, logic gates, solar cells and light emitting diodes. Use of Gallium Nitride (GaN) and other wide bandgap materials combines the advantages of III-nitrides along with the enhanced mobility offered by 2-dimensional confinement present in nanowires. The focus of this thesis is on developing a low field mobility model for a GaN nanowire using Ensemble Monte Carlo (EMC) techniques. A 2D Schrödinger-Poisson solver and a one-dimensional Monte Carlo solver is developed for an Aluminum Gallium Nitride/Gallium Nitride Heterostructure nanowire. A GaN/AlN/AlGaN heterostructure device is designed which creates 2-dimensional potential well for electrons. The nanowire is treated as a quasi-1D system in this work. A self-consistent 2D Schrödinger-Poisson solver is designed which determines the subband energies and the corresponding wavefunctions of the confined system. Three scattering mechanisms: acoustic phonon scattering, polar optical phonon scattering and piezoelectric scattering are considered to account for the electron phonon interactions in the system. Overlap integrals and 1D scattering rate expressions are derived for all the mechanisms listed. A generic one-dimensional Monte Carlo solver is also developed. Steady state results from the 1D Monte Carlo solver are extracted to determine the low field mobility of the GaN nanowires.
ContributorsKumar, Viswanathan Naveen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Zhao, Yuji (Committee member) / Arizona State University (Publisher)
Created2017
Fill Factor Loss Mechanisms: Analysis and Basic Understanding in Silicon Hetero-junction Solar Cells
Description
The objective of this thesis is to achieve a detailed understanding of the loss mechanisms in SHJ solar cells. The working principles of these cells and what affects the cell operation, e.g. the IV characteristics at the maximum power point (MPP) and the correspondingly ll factor (FF) are investigated. Dierent loss sources are analyzed separately, and the weight of each in the total loss at the MPP are evaluated. The total series resistance is measured and then compared with the value obtained through summation over each of its components. In other words, series resistance losses due to recombination, vertical and lateral carrier transport, metalization, etc, are individually evaluated, and then by adding all these components together, the total loss is calculated. The concept of ll factor and its direct dependence on the loss mechanisms at the MPP of the device is explained, and its sensitivity to nearly every processing step of the cell fabrication is investigated. This analysis provides a focus lens to identify the main source of losses in SHJ solar cells and pave the path for further improvements in cell efficiency.
In this thesis, we provide a detailed understanding of the FF concept; we explain how it can be directly measured; how it can be calculated and what expressions can better approximate its value and under what operating conditions. The relation between FF and cell operating condition at the MPP is investigated. We separately analyzed the main FF sources of losses including recombination, sheet resistance, contact resistance and metalization. We study FF loss due to recombination and its separate components which include the Augur, radiative and SRH recombination is investigated. We study FF loss due to contact resistance and its separate components which include the contact resistance of dierent interfaces, e.g. between the intrinsic and doped a-Si layers, TCO and a-Si layers. We also study FF loss due to lateral transport and its components that including the TCO sheet resistance, the nger and the busbars resistances.
In this thesis, we provide a detailed understanding of the FF concept; we explain how it can be directly measured; how it can be calculated and what expressions can better approximate its value and under what operating conditions. The relation between FF and cell operating condition at the MPP is investigated. We separately analyzed the main FF sources of losses including recombination, sheet resistance, contact resistance and metalization. We study FF loss due to recombination and its separate components which include the Augur, radiative and SRH recombination is investigated. We study FF loss due to contact resistance and its separate components which include the contact resistance of dierent interfaces, e.g. between the intrinsic and doped a-Si layers, TCO and a-Si layers. We also study FF loss due to lateral transport and its components that including the TCO sheet resistance, the nger and the busbars resistances.
ContributorsLeilaeioun, Mohammadmehdi (Ashling) (Author) / Goodnick, Stephen (Thesis advisor) / Goryll, Michael (Thesis advisor) / Bertoni, Mariana (Committee member) / Bowden, Stuart (Committee member) / Stuckelberger, Michael (Committee member) / Arizona State University (Publisher)
Created2018
Description
Achieving high efficiency in solar cells requires optimal photovoltaics materials for light absorption and as with any electrical device—high-quality contacts. Essentially, the contacts separate the charge carriers—holes at one terminal and electrons at the other—extracting them to an external circuit. For this purpose, the development of passivating and carrier-selective contacts that enable low interface defect density and efficient carrier transport is critical for making high-efficiency solar cells. The recent record-efficiency n-type silicon cells with hydrogenated amorphous silicon (a-Si:H) contacts have demonstrated the usefulness of passivating and carrier-selective contacts. However, the use of a-Si:H contacts should not be limited in just n-type silicon cells.
In the present work, a-Si:H contacts for crystalline silicon and cadmium telluride (CdTe) solar cells are developed. First, hydrogen-plasma-processsed a-Si:H contacts are used in n-type Czochralski silicon cell fabrication. Hydrogen plasma treatment is used to increase the Si-H bond density of a-Si:H films and decrease the dangling bond density at the interface, which leads to better interface passivation and device performance, and wider temperature-processing window of n-type silicon cells under full spectrum (300–1200 nm) illumination. In addition, thickness-varied a-Si:H contacts are studied for n-type silicon cells under the infrared spectrum (700–1200 nm) illumination, which are prepared for silicon-based tandem applications.
Second, the a-Si:H contacts are applied to commercial-grade p-type silicon cells, which have much lower bulk carrier lifetimes than the n-type silicon cells. The approach is using gettering and bulk hydrogenation to improve the p-type silicon bulk quality, and then applying a-Si:H contacts to enable excellent surface passivation and carrier transport. This leads to an open-circuit voltage of 707 mV in p-type Czochralski silicon cells, and of 702 mV, the world-record open-circuit voltage in p-type multi-crystalline silicon cells.
Finally, CdTe cells with p-type a-Si:H hole-selective contacts are studied. As a proof of concept, p-type a-Si:H contacts enable achieving the highest reported open-circuit voltages (1.1 V) in mono-crystalline CdTe devices. A comparative study of applying p-type a-Si:H contacts in poly-crystalline CdTe solar cells is performed, resulting in absolute voltage gain of 53 mV over using the standard tellurium contacts.
In the present work, a-Si:H contacts for crystalline silicon and cadmium telluride (CdTe) solar cells are developed. First, hydrogen-plasma-processsed a-Si:H contacts are used in n-type Czochralski silicon cell fabrication. Hydrogen plasma treatment is used to increase the Si-H bond density of a-Si:H films and decrease the dangling bond density at the interface, which leads to better interface passivation and device performance, and wider temperature-processing window of n-type silicon cells under full spectrum (300–1200 nm) illumination. In addition, thickness-varied a-Si:H contacts are studied for n-type silicon cells under the infrared spectrum (700–1200 nm) illumination, which are prepared for silicon-based tandem applications.
Second, the a-Si:H contacts are applied to commercial-grade p-type silicon cells, which have much lower bulk carrier lifetimes than the n-type silicon cells. The approach is using gettering and bulk hydrogenation to improve the p-type silicon bulk quality, and then applying a-Si:H contacts to enable excellent surface passivation and carrier transport. This leads to an open-circuit voltage of 707 mV in p-type Czochralski silicon cells, and of 702 mV, the world-record open-circuit voltage in p-type multi-crystalline silicon cells.
Finally, CdTe cells with p-type a-Si:H hole-selective contacts are studied. As a proof of concept, p-type a-Si:H contacts enable achieving the highest reported open-circuit voltages (1.1 V) in mono-crystalline CdTe devices. A comparative study of applying p-type a-Si:H contacts in poly-crystalline CdTe solar cells is performed, resulting in absolute voltage gain of 53 mV over using the standard tellurium contacts.
ContributorsShi, Jianwei (Author) / Holman, Zachary (Thesis advisor) / Bowden, Stuart (Committee member) / Bertoni, Mariana (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2018
Description
Gallium Nitride (GaN) based Current Aperture Vertical Electron Transistors (CAVETs) present many appealing qualities for applications in high power, high frequency devices. The wide bandgap, high carrier velocity of GaN make it ideal for withstanding high electric fields and supporting large currents. The vertical topology of the CAVET allows for more efficient die area utilization, breakdown scaling with the height of the device, and burying high electric fields in the bulk where they will not charge interface states that can lead to current collapse at higher frequency.
Though GaN CAVETs are promising new devices, they are expensive to develop due to new or exotic materials and processing steps. As a result, the accurate simulation of GaN CAVETs has become critical to the development of new devices. Using Silvaco Atlas 5.24.1.R, best practices were developed for GaN CAVET simulation by recreating the structure and results of the pGaN insulated gate CAVET presented in chapter 3 of [8].
From the results it was concluded that the best simulation setup for transfer characteristics, output characteristics, and breakdown included the following. For methods, the use of Gummel, Block, Newton, and Trap. For models, SRH, Fermi, Auger, and impact selb. For mobility, the use of GANSAT and manually specified saturation velocity and mobility (based on doping concentration). Additionally, parametric sweeps showed that, of those tested, critical CAVET parameters included channel mobility (and thus doping), channel thickness, Current Blocking Layer (CBL) doping, gate overlap, and aperture width in rectangular devices or diameter in cylindrical devices.
Though GaN CAVETs are promising new devices, they are expensive to develop due to new or exotic materials and processing steps. As a result, the accurate simulation of GaN CAVETs has become critical to the development of new devices. Using Silvaco Atlas 5.24.1.R, best practices were developed for GaN CAVET simulation by recreating the structure and results of the pGaN insulated gate CAVET presented in chapter 3 of [8].
From the results it was concluded that the best simulation setup for transfer characteristics, output characteristics, and breakdown included the following. For methods, the use of Gummel, Block, Newton, and Trap. For models, SRH, Fermi, Auger, and impact selb. For mobility, the use of GANSAT and manually specified saturation velocity and mobility (based on doping concentration). Additionally, parametric sweeps showed that, of those tested, critical CAVET parameters included channel mobility (and thus doping), channel thickness, Current Blocking Layer (CBL) doping, gate overlap, and aperture width in rectangular devices or diameter in cylindrical devices.
ContributorsWarren, Andrew (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Zhao, Yuji (Committee member) / Arizona State University (Publisher)
Created2019
Description
Wide bandgap (WBG) semiconductors GaN (3.4 eV), Ga2O3 (4.8 eV) and AlN (6.2 eV), have gained considerable interests for energy-efficient optoelectronic and electronic applications in solid-state lighting, photovoltaics, power conversion, and so on. They can offer unique device performance compared with traditional semiconductors such as Si. Efficient GaN based light-emitting diodes (LEDs) have increasingly displaced incandescent and fluorescent bulbs as the new major light sources for lighting and display. In addition, due to their large bandgap and high critical electrical field, WBG semiconductors are also ideal candidates for efficient power conversion.
In this dissertation, two types of devices are demonstrated: optoelectronic and electronic devices. Commercial polar c-plane LEDs suffer from reduced efficiency with increasing current densities, knowns as “efficiency droop”, while nonpolar/semipolar LEDs exhibit a very low efficiency droop. A modified ABC model with weak phase space filling effects is proposed to explain the low droop performance, providing insights for designing droop-free LEDs. The other emerging optoelectronics is nonpolar/semipolar III-nitride intersubband transition (ISBT) based photodetectors in terahertz and far infrared regime due to the large optical phonon energy and band offset, and the potential of room-temperature operation. ISBT properties are systematically studied for devices with different structures parameters.
In terms of electronic devices, vertical GaN p-n diodes and Schottky barrier diodes (SBDs) with high breakdown voltages are homoepitaxially grown on GaN bulk substrates with much reduced defect densities and improved device performance. The advantages of the vertical structure over the lateral structure are multifold: smaller chip area, larger current, less sensitivity to surface states, better scalability, and smaller current dispersion. Three methods are proposed to boost the device performances: thick buffer layer design, hydrogen-plasma based edge termination technique, and multiple drift layer design. In addition, newly emerged Ga2O3 and AlN power electronics may outperform GaN devices. Because of the highly anisotropic crystal structure of Ga2O3, anisotropic electrical properties have been observed in Ga2O3 electronics. The first 1-kV-class AlN SBDs are demonstrated on cost-effective sapphire substrates. Several future topics are also proposed including selective-area doping in GaN power devices, vertical AlN power devices, and (Al,Ga,In)2O3 materials and devices.
In this dissertation, two types of devices are demonstrated: optoelectronic and electronic devices. Commercial polar c-plane LEDs suffer from reduced efficiency with increasing current densities, knowns as “efficiency droop”, while nonpolar/semipolar LEDs exhibit a very low efficiency droop. A modified ABC model with weak phase space filling effects is proposed to explain the low droop performance, providing insights for designing droop-free LEDs. The other emerging optoelectronics is nonpolar/semipolar III-nitride intersubband transition (ISBT) based photodetectors in terahertz and far infrared regime due to the large optical phonon energy and band offset, and the potential of room-temperature operation. ISBT properties are systematically studied for devices with different structures parameters.
In terms of electronic devices, vertical GaN p-n diodes and Schottky barrier diodes (SBDs) with high breakdown voltages are homoepitaxially grown on GaN bulk substrates with much reduced defect densities and improved device performance. The advantages of the vertical structure over the lateral structure are multifold: smaller chip area, larger current, less sensitivity to surface states, better scalability, and smaller current dispersion. Three methods are proposed to boost the device performances: thick buffer layer design, hydrogen-plasma based edge termination technique, and multiple drift layer design. In addition, newly emerged Ga2O3 and AlN power electronics may outperform GaN devices. Because of the highly anisotropic crystal structure of Ga2O3, anisotropic electrical properties have been observed in Ga2O3 electronics. The first 1-kV-class AlN SBDs are demonstrated on cost-effective sapphire substrates. Several future topics are also proposed including selective-area doping in GaN power devices, vertical AlN power devices, and (Al,Ga,In)2O3 materials and devices.
ContributorsFu, Houqiang (Author) / Zhao, Yuji (Thesis advisor) / Vasileska, Dragica (Committee member) / Goodnick, Stephen (Committee member) / Yu, Hongbin (Committee member) / Wang, Liping (Committee member) / Arizona State University (Publisher)
Created2019
Description
Moore's law has been the most important driving force for the tremendous progress of semiconductor industry. With time the transistors which form the fundamental building block of any integrated circuit have been shrinking in size leading to smaller and faster electronic devices.As the devices scale down thermal effects and the short channel effects become the important deciding factors in determining transistor architecture.SOI (Silicon on Insulator) devices have been excellent alternative to planar MOSFET for ultimate CMOS scaling since they mitigate short channel effects. Hence as a part of thesis we tried to study the benefits of the SOI technology especially for lower technology nodes when the channel thickness reduces down to sub 10nm regime. This work tries to explore the effects of structural confinement due to reduced channel thickness on the electrostatic behavior of DG SOI MOSFET. DG SOI MOSFET form the Qfinfet which is an alternative to existing Finfet structure. Qfinfet was proposed and patented by the Finscale Inc for sub 10nm technology nodes.
As part of MS Thesis we developed electrostatic simulator for DG SOI devices by implementing the self consistent full band Schrodinger Poisson solver. We used the Empirical Pseudopotential method in conjunction with supercell approach to solve the Schrodinger Equation. EPM was chosen because it has few empirical parameters which give us good accuracy for experimental results. Also EPM is computationally less expensive as compared to the atomistic methods like DFT(Density functional theory) and NEGF (Non-equilibrium Green's function). In our workwe considered two crystallographic orientations of Si,namely [100] and [110].
As part of MS Thesis we developed electrostatic simulator for DG SOI devices by implementing the self consistent full band Schrodinger Poisson solver. We used the Empirical Pseudopotential method in conjunction with supercell approach to solve the Schrodinger Equation. EPM was chosen because it has few empirical parameters which give us good accuracy for experimental results. Also EPM is computationally less expensive as compared to the atomistic methods like DFT(Density functional theory) and NEGF (Non-equilibrium Green's function). In our workwe considered two crystallographic orientations of Si,namely [100] and [110].
ContributorsLaturia, Akash (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2016