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- All Subjects: Electrical Engineering
- Creators: Ozev, Sule
- Resource Type: Text
- Status: Published
Description
Internet of Things (IoT) has become a popular topic in industry over the recent years, which describes an ecosystem of internet-connected devices or things that enrich the everyday life by improving our productivity and efficiency. The primary components of the IoT ecosystem are hardware, software and services. While the software and services of IoT system focus on data collection and processing to make decisions, the underlying hardware is responsible for sensing the information, preprocess and transmit it to the servers. Since the IoT ecosystem is still in infancy, there is a great need for rapid prototyping platforms that would help accelerate the hardware design process. However, depending on the target IoT application, different sensors are required to sense the signals such as heart-rate, temperature, pressure, acceleration, etc., and there is a great need for reconfigurable platforms that can prototype different sensor interfacing circuits.
This thesis primarily focuses on two important hardware aspects of an IoT system: (a) an FPAA based reconfigurable sensing front-end system and (b) an FPGA based reconfigurable processing system. To enable reconfiguration capability for any sensor type, Programmable ANalog Device Array (PANDA), a transistor-level analog reconfigurable platform is proposed. CAD tools required for implementation of front-end circuits on the platform are also developed. To demonstrate the capability of the platform on silicon, a small-scale array of 24×25 PANDA cells is fabricated in 65nm technology. Several analog circuit building blocks including amplifiers, bias circuits and filters are prototyped on the platform, which demonstrates the effectiveness of the platform for rapid prototyping IoT sensor interfaces.
IoT systems typically use machine learning algorithms that run on the servers to process the data in order to make decisions. Recently, embedded processors are being used to preprocess the data at the energy-constrained sensor node or at IoT gateway, which saves considerable energy for transmission and bandwidth. Using conventional CPU based systems for implementing the machine learning algorithms is not energy-efficient. Hence an FPGA based hardware accelerator is proposed and an optimization methodology is developed to maximize throughput of any convolutional neural network (CNN) based machine learning algorithm on a resource-constrained FPGA.
This thesis primarily focuses on two important hardware aspects of an IoT system: (a) an FPAA based reconfigurable sensing front-end system and (b) an FPGA based reconfigurable processing system. To enable reconfiguration capability for any sensor type, Programmable ANalog Device Array (PANDA), a transistor-level analog reconfigurable platform is proposed. CAD tools required for implementation of front-end circuits on the platform are also developed. To demonstrate the capability of the platform on silicon, a small-scale array of 24×25 PANDA cells is fabricated in 65nm technology. Several analog circuit building blocks including amplifiers, bias circuits and filters are prototyped on the platform, which demonstrates the effectiveness of the platform for rapid prototyping IoT sensor interfaces.
IoT systems typically use machine learning algorithms that run on the servers to process the data in order to make decisions. Recently, embedded processors are being used to preprocess the data at the energy-constrained sensor node or at IoT gateway, which saves considerable energy for transmission and bandwidth. Using conventional CPU based systems for implementing the machine learning algorithms is not energy-efficient. Hence an FPGA based hardware accelerator is proposed and an optimization methodology is developed to maximize throughput of any convolutional neural network (CNN) based machine learning algorithm on a resource-constrained FPGA.
ContributorsSuda, Naveen (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Yu, Shimeng (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016
Description
Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented employs a comparator inside the traditional circuit to reduce the value of the time constant needed. The second circuit uses a dynamic time constant approach in which the value of the time constant is dynamically adjusted after the clamp is triggered. Important metrics for the two new circuits such as ESD performance, latch-on immunity, clamp recovery time, supply noise immunity, fastest power-on time supported, and area are evaluated over an industry-standard PVT space using SPICE simulations and measurements on a fabricated 40 nm test chip.
ContributorsVenkatasubramanian, Ramachandran (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2016
Description
The efficiency of spacecraft’s solar cells reduces over the course of their operation. Traditionally, they are configured to extract maximum power at the end of their life and not have a system which dynamically extracts the maximum power over their entire life. This work demonstrates the benefit of dynamic re-configuration of spacecraft’s solar arrays to access the full power available from the solar panels throughout their lifetime. This dynamic re-configuration is achieved using enhancement mode GaN devices as the switches due to their low Ron and small footprint.
This work discusses hardware Implementation challenges and a prototype board is designed using components-off-the-shelf (COTS) to study the behavior of photovoltaic (PV) panels with different configurations of switches between 5 PV cells. The measurement results from the board proves the feasibility of the idea, showing the power improvements of having the switch structure. The measurement results are used to simulate a 1kW satellite system and understand practical trade-offs of this idea in actual satellite power systems.
Additionally, this work also presents the implementation of CMOS controller integrated circuit (IC) in 0.18um technology. The CMOS controller IC includes switched-capacitor converters in open loop to provide the floating voltages required to drive the GaN switches. Each CMOS controller IC can drive 10 switches in series and parallel combination. Furthermore, the designed controller IC is expected to operate under 300MRad of total dose radiation, thus enabling the controller modules to be placed on the solar cell wings of the satellites.
This work discusses hardware Implementation challenges and a prototype board is designed using components-off-the-shelf (COTS) to study the behavior of photovoltaic (PV) panels with different configurations of switches between 5 PV cells. The measurement results from the board proves the feasibility of the idea, showing the power improvements of having the switch structure. The measurement results are used to simulate a 1kW satellite system and understand practical trade-offs of this idea in actual satellite power systems.
Additionally, this work also presents the implementation of CMOS controller integrated circuit (IC) in 0.18um technology. The CMOS controller IC includes switched-capacitor converters in open loop to provide the floating voltages required to drive the GaN switches. Each CMOS controller IC can drive 10 switches in series and parallel combination. Furthermore, the designed controller IC is expected to operate under 300MRad of total dose radiation, thus enabling the controller modules to be placed on the solar cell wings of the satellites.
ContributorsHeblikar, Anand N (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2019
Description
With the steady advancement of neural network research, new applications are continuously emerging. As a tool for test time reduction, neural networks provide a reliable method of identifying and applying correlations in datasets to speed data processing. By leveraging the power of a deep neural net, it is possible to record the motion of an accelerometer in response to an electrical stimulus and correlate the response with a trim code to reduce the total test time for such sensors. This reduction can be achieved by replacing traditional trimming methods such as physical shaking or mathematical models with a neural net that is able to process raw sensor data collected with the help of a microcontroller. With enough data, the neural net can process the raw responses in real time to predict the correct trim codes without requiring any additional information. Though not yet a complete replacement, the method shows promise given more extensive datasets and industry-level testing and has the potential to disrupt the current state of testing.
ContributorsDebeurre, Nicholas (Author) / Ozev, Sule (Thesis advisor) / Vrudhula, Sarma (Thesis advisor) / Kniffin, Margaret (Committee member) / Arizona State University (Publisher)
Created2019
Description
Micro Electro Mechanical Systems (MEMS) based accelerometers are one of the most commonly used sensors out there. They are used in devices such as, airbags, smartphones, airplanes, and many more. Although they are very accurate, they degrade with time or get offset due to some damage. To fix this, they must be calibrated again using physical calibration technique, which is an expensive process to conduct. However, these sensors can also be calibrated infield by applying an on-chip electrical stimulus to the sensor. Electrical stimulus-based calibration could bring the cost of testing and calibration significantly down as compared to factory testing. In this thesis, simulations are presented to formulate a statistical prediction model based on an electrical stimulus. Results from two different approaches of electrical calibration have been discussed. A prediction model with a root mean square error of 1% has been presented in this work. Experiments were conducted on commercially available accelerometers to test the techniques used for simulations.
ContributorsBassi, Ishaan (Author) / Ozev, Sule (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2020
Description
This work analyzes and develops a point-of-load (PoL) synchronous buck converter using enhancement-mode Gallium Nitride (e-GaN), with emphasis on optimizing reverse conduction loss by using a well-known technique of placing an anti-parallel Schottky diode across the synchronous power device. This work develops an improved analytical switching model for the GaN-based converter with the Schottky diode using piecewise linear approximations.
To avoid a shoot-through between the power switches of the buck converter, a small dead-time is inserted between gate drive switching transitions. Despite optimum dead-time management for a power converter, optimum dead-times vary for different load conditions. These variations become considerably large for PoL applications, which demand high output current with low output voltages. At high switching frequencies, these variations translate into losses that contribute significantly to the total loss of the converter. To understand and quantify power loss in a hard-switching buck converter that uses a GaN power device in parallel with a Schottky diode, piecewise transitions are used to develop an analytical switching model that quantifies the contribution of reverse conduction loss of GaN during dead-time.
The effects of parasitic elements on the dynamics of the switching converter are investigated during one switching cycle of the converter. A designed prototype of a buck converter is correlated to the predicted model to determine the accuracy of the model. This comparison is presented using simulations and measurements at 400 kHz and 2 MHz converter switching speeds for load (1A) condition and fixed dead-time values. Furthermore, performance of the buck converter with and without the Schottky diode is also measured and compared to demonstrate and quantify the enhanced performance when using an anti-parallel diode. The developed power converter achieves peak efficiencies of 91.7% and 93.86% for 2 MHz and 400 KHz switching frequencies, respectively, and drives load currents up to 6A for a voltage conversion from 12V input to 3.3V output.
In addition, various industry Schottky diodes have been categorized based on their packaging and electrical characteristics and the developed analytical model provides analytical expressions relating the diode characteristics to power stage performance parameters. The performance of these diodes has been characterized for different buck converter voltage step-down ratios that are typically used in industry applications and different switching frequencies ranging from 400 KHz to 2 MHz.
To avoid a shoot-through between the power switches of the buck converter, a small dead-time is inserted between gate drive switching transitions. Despite optimum dead-time management for a power converter, optimum dead-times vary for different load conditions. These variations become considerably large for PoL applications, which demand high output current with low output voltages. At high switching frequencies, these variations translate into losses that contribute significantly to the total loss of the converter. To understand and quantify power loss in a hard-switching buck converter that uses a GaN power device in parallel with a Schottky diode, piecewise transitions are used to develop an analytical switching model that quantifies the contribution of reverse conduction loss of GaN during dead-time.
The effects of parasitic elements on the dynamics of the switching converter are investigated during one switching cycle of the converter. A designed prototype of a buck converter is correlated to the predicted model to determine the accuracy of the model. This comparison is presented using simulations and measurements at 400 kHz and 2 MHz converter switching speeds for load (1A) condition and fixed dead-time values. Furthermore, performance of the buck converter with and without the Schottky diode is also measured and compared to demonstrate and quantify the enhanced performance when using an anti-parallel diode. The developed power converter achieves peak efficiencies of 91.7% and 93.86% for 2 MHz and 400 KHz switching frequencies, respectively, and drives load currents up to 6A for a voltage conversion from 12V input to 3.3V output.
In addition, various industry Schottky diodes have been categorized based on their packaging and electrical characteristics and the developed analytical model provides analytical expressions relating the diode characteristics to power stage performance parameters. The performance of these diodes has been characterized for different buck converter voltage step-down ratios that are typically used in industry applications and different switching frequencies ranging from 400 KHz to 2 MHz.
ContributorsKoli, Gauri (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2020
Description
The manufacturing process for electronic systems involves many players, from chip/board design and fabrication to firmware design and installation.
In today's global supply chain, any of these steps are prone to interference from rogue players, creating a security risk.
Manufactured devices need to be verified to perform only their intended operations since it is not economically feasible to control the supply chain and use only trusted facilities.
It is becoming increasingly necessary to trust but verify the received devices both at production and in the field.
Unauthorized hardware or firmware modifications, known as Trojans,
can steal information, drain the battery, or damage battery-driven embedded systems and lightweight Internet of Things (IoT) devices.
Since Trojans may be triggered in the field at an unknown instance,
it is essential to detect their presence at run-time.
However, it isn't easy to run sophisticated detection algorithms on these devices
due to limited computational power and energy, and in some cases, lack of accessibility.
Since finding a trusted sample is infeasible in general, the proposed technique is based on self-referencing to remove any effect of environmental or device-to-device variations in the frequency domain.
In particular, the self-referencing is achieved by exploiting the band-limited nature of Trojan activity using signal detection theory.
When the device enters the test mode, a predefined test application is run on the device
repetitively for a known period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operating bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicate the presence of unknown (unauthorized) activity. Hence, the malicious activity can differentiate without using a golden reference or any knowledge of the Trojan activity attributes.
The proposed technique's effectiveness is demonstrated through experiments with collecting and processing side-channel signals, such as involuntarily electromagnetic emissions and power consumption, of a wearable electronics prototype and commercial system-on-chip under a variety of practical scenarios.
In today's global supply chain, any of these steps are prone to interference from rogue players, creating a security risk.
Manufactured devices need to be verified to perform only their intended operations since it is not economically feasible to control the supply chain and use only trusted facilities.
It is becoming increasingly necessary to trust but verify the received devices both at production and in the field.
Unauthorized hardware or firmware modifications, known as Trojans,
can steal information, drain the battery, or damage battery-driven embedded systems and lightweight Internet of Things (IoT) devices.
Since Trojans may be triggered in the field at an unknown instance,
it is essential to detect their presence at run-time.
However, it isn't easy to run sophisticated detection algorithms on these devices
due to limited computational power and energy, and in some cases, lack of accessibility.
Since finding a trusted sample is infeasible in general, the proposed technique is based on self-referencing to remove any effect of environmental or device-to-device variations in the frequency domain.
In particular, the self-referencing is achieved by exploiting the band-limited nature of Trojan activity using signal detection theory.
When the device enters the test mode, a predefined test application is run on the device
repetitively for a known period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operating bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicate the presence of unknown (unauthorized) activity. Hence, the malicious activity can differentiate without using a golden reference or any knowledge of the Trojan activity attributes.
The proposed technique's effectiveness is demonstrated through experiments with collecting and processing side-channel signals, such as involuntarily electromagnetic emissions and power consumption, of a wearable electronics prototype and commercial system-on-chip under a variety of practical scenarios.
ContributorsKarabacak, Fatih (Author) / Ozev, Sule (Thesis advisor) / Ogras, Umit Y. (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2020
Description
Point-of-Care diagnostics is one of the most popular fields of research in bio-medicine today because of its portability, speed of response, convenience and quality assurance. One of the most important steps in such a device is to prepare and purify the sample by extracting the nucleic acids, for which small spherical magnetic particles called magnetic beads are often used in laboratories. Even though magnetic beads have the ability to isolate DNA or RNA from bio-samples in their purified form, integrating these into a microfluidic point-of-need testing kit is still a bit of a challenge. In this thesis, the possibility of integrating paramagnetic beads instead of silica-coated dynabeads, has been evaluated with respect to a point-of-need SARS-CoV-2 virus testing kit. This project is a comparative study between five different sizes of carboxyl-coated paramagnetic beads with reference to silica-coated dynabeads, and how each of them behave in a microcapillary chip in presence of magnetic fields of different strengths. The diameters and velocities of the beads have been calculated using different types of microscopic imaging techniques. The washing and elution steps of an extraction process have been recreated using syringe pump, microcapillary channels and permanent magnets, based on which those parameters of the beads have been studied which are essential for extraction behaviour. The yield efficiency of the beads have also been analysed by using these to extract Salmon DNA. Overall, furthering this research will improve the sensitivity and specificity for any low-cost nucleic-acid based point-of-care testing device.
ContributorsBiswas, Shilpita (Author) / Christen, Jennifer B (Thesis advisor) / Ozev, Sule (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2021
Description
Impedance is one of the fundamental properties of electrical components, materials, and waves. Therefore, impedance measurement and monitoring have a wide range of applications. The multi-port technique is a natural candidate for impedance measurement and monitoring due to its low overhead and ease of implementation for Built-in Self-Test (BIST) applications. The multi-port technique can measure complex reflection coefficients, thus impedance, by using scalar measurements provided by the power detectors. These power detectors are strategically placed on different points (ports) of a passive network to produce unique solution. Impedance measurement and monitoring is readily deployed on mobile phone radio-frequency (RF) front ends, and are combined with antenna tuners to boost the signal reception capabilities of phones. These sensors also can be used in self-healing circuits to improve their yield and performance under process, voltage, and temperature variations. Even though, this work is preliminary interested in low-overhead impedance measurement for RF circuit applications, the proposed methods can be used in a wide variety of metrology applications where impedance measurements are already used. Some examples of these applications include determining material properties, plasma generation, and moisture detection. Additionally, multi-port applications extend beyond the impedance measurement. There are applications where multi-ports are used as receivers for communication systems, RADARs, and remote sensing applications. The multi-port technique generally requires a careful design of the testing structure to produce a unique solution from power detector measurements. It also requires the use of nonlinear solvers during calibration, and depending on calibration procedure, measurement. The use of nonlinear solvers generates issues for convergence, computational complexity, and resources needed for carrying out calibrations and measurements in a timely manner. In this work, using periodic structures, a structure where a circuit block repeats itself, for multi-port measurements is proposed. The periodic structures introduce a new constraint that simplifies the multi-port theory and leads to an explicit calibration and measurement procedure. Unlike the existing calibration procedures which require at least five loads and various constraints on the load for explicit solution, the proposed method can use three loads for calibration. Multi-ports built with periodic structures will always produce a unique measurement result. This leads to increased bandwidth of operation and simplifies design procedure. The efficacy of the method demonstrated in two embodiments.
In the first embodiment, a multi-port is directly embedded into a matching network to measure impedance of the load.
In the second embodiment, periodic structures are used to compare two loads without requiring any calibration.
ContributorsAvci, Muslum Emir (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Trichopoulos, Georgios (Committee member) / Arizona State University (Publisher)
Created2023
Description
This work presents two balanced power amplifier (PA) architectures, one at X-band and the other at K-band. The presented balanced PAs are designed for use in small satellite and cube satellite applications.The presented X-band PA employs wideband hybrid couplers to split input power to two commercial off-the-shelf (COTS) Gallium Nitride (GaN) monolithic microwave integrated circuit (MMIC) PAs and combine their output powers. The presented X-band balanced PA manufactured on a Rogers 4003C substrate yields increased small signal gain and saturated output power under continuous wave (CW) operation compared to the single MMIC PA used in the design under pulsed operation. The presented PA operates from 7.5 GHz to 11.5 GHz, has a maximum small signal gain of 36.3 dB, a maximum saturated power out of 40.0 dBm, and a maximum power added efficiency (PAE) of 38%.
Both a Wilkinson and a Gysel splitter and combiner are designed for use at K-band and their performance is compared. The presented K-band balanced PA uses Gysel power dividers and combiners with a GaN MMIC PA that is soon to be released in production.
ContributorsPearson, Katherine Elizabeth (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2023