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Description
The project described here is a solar powered intrusion detection system consisting of three modules: a battery recharging circuit, a laser emitter and photodetector pair, and a Wi- Fi connectivity board. Over the preceding seven months, great care has been taken for the design and construction of this system. The first three months were spent researching and selecting suitable IC's and external components (e.g. solar panel, batteries, etc.). Then, the next couple of months were spent ordering specific materials and equipment for the construction of our prototype. Finally, the last two months were used to build a working prototype, with a substantial amount of time used for perfecting our system's packaging and operation. This report will consist of a detailed discussion of our team's research, design activities, prototype implementation, final budget, and final schedule. Technical discussion of the concepts behind our design will assist with understanding the design activities and prototype implementation sections that will follow. Due to the generous funding of the group from the Barrett Honors College, our overall budget available for the project was $1600. Of that amount, only $334.51 was spent on the actual system components, with $829.42 being spent on the equipment and materials needed for the testing and construction of the prototype. As far as the schedule goes, we are essentially done with the project. The only tasks left to finish are a successful defense of the project at the oral presentation on Friday, 29 March 2013, followed by a successful demo on 26 April 2013.
ContributorsTroyer, Nicole L. (Co-author) / Shtayer, Idan (Co-author) / Guise, Chris (Co-author) / Kozicki, Michael (Thesis director) / Roedel, Ronald (Committee member) / Goodnick, Stephen (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2013-05
Description
The apparent phenomenon of the human eye retaining images for fractions of a second after the light source has gone is known as Persistence of Vision. While its causes are not fully understood, it can be taken advantage of in order to create illusions which trick the mind into perceiving something which, in actuality, is very different from what the mind portrays. It has motivated many creative engineering technologies in the past and is the core for how we perceive motion in movies and animations. This project applies the persistence of vision concept to a lesser explored medium; the wheel of a moving bicycle. The motion of the wheel, along with intelligent control of discrete LEDs, create vibrant illusions of solid lines and shapes. These shapes make up the image to be displayed on the bike wheel. The rotation of the bike wheel can be compensated for in order to produce a standing image (or images) of the user's choosing. This thesis details how the mechanism for conducting the individual LEDs was created in order to produce a device which is capable of delivering colorful, standing images of the user's choosing.
ContributorsSaltwick, Ian Mark (Author) / Goryll, Michael (Thesis director) / Kozicki, Michael (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
This is a test plan document for Team Aegis' capstone project that has the goal of mitigating single event upsets in NAND flash memory caused by space radiation.
ContributorsForman, Oliver Ethan (Co-author) / Smith, Aiden (Co-author) / Salls, Demetra (Co-author) / Kozicki, Michael (Thesis director) / Hodge, Chris (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
Recently, the implementation of neuromorphic accelerator hardware has gradually changed from traditional Von Neumann architectures to non-Von Neumann architectures due to the “memory wall” and “power wall”. Near-memory computing (NMC) and In- memory computing (IMC) are two common types of non-Von Neumann approaches. NMC can help reduce data movements, yet it cannot fully address the challenge of improving computational efficiency as the neural network size grows. IMC has been proposed as a superior alternative. This architecture performs computation inside the memory array using stackable synaptic devices to improve the latency and the energy efficiency of neural network accelerators. Both volatile and non-volatile computational memory devices can achieve IMC. Fully complementary metal-oxide semiconductor (CMOS) in-memory computing cells can be realized by adding additional transistors in standard static random access memory (SRAM) bit-cell. The SRAM-based designs investigated in this dissertation perform bit-wise logical operation to obtain XNOR-and-accumulate computation (XAC) for deep neural networks (DNNs). Hybrid in-memory computing architectures combine CMOS with embedded non-volatile memory (eNVM). Resistive random access memory (RRAM) is one class of eNVM ideally suited for hybrid IMC. In a neural network, RRAM with programmable multi-level resistance/conductance states can naturally emulate weight transitions in the synaptic elements of neural networks. In this dissertation, the operation and effects of ionizing radiation effects on both fully CMOS and hybrid IMCs are investigated. The fully CMOS architectures preform SRAM-based XAC computations. The hybrid architectures use multi-state RRAM synapse with CMOS neurons to perform multiply-and-accumulate computation (MAC). In the SRAM XAC array, an 8×8 XNOR IMC array is modeled with flipped-well enhanced-gate super low threshold voltage (EGSLVT) metal-oxide semiconductor field-effect transistors (MOSFETs) from the GlobalFoundries 22nm fully depleted silicon on insulator (FDSOI) process. The impact of total ionizing dose (TID) on the XAC synaptic array is analyzed by using radiation-aware models to mimic TID-induced voltage shifts in MOSFETs. In multi- state RRAM MAC array, 4-state conductance has been programmed in hafnium-oxide (HfOx) RRAM 1-transistor-1-resistor (1T1R) array. The impact of total ionizing dose on the multi-state behavior of HfOx RRAM is evaluated by irradiating a 64kb 1T1R array with 90nm CMOS peripheral circuitry under Co-60 γ-ray irradiation.
ContributorsHan, Xu (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Marinella, Matthew (Committee member) / Esqueda, Ivan (Committee member) / Arizona State University (Publisher)
Created2022
Description
The Deep Neural Network (DNN) is one type of a neuromorphic computing approach that has gained substantial interest today. To achieve continuous improvement in accuracy, the depth, and the size of the deep neural network needs to significantly increase. As the scale of the neural network increases, it poses a severe challenge to its hardware implementation with conventional Computer Processing Unit (CPU) and Graphic Processing Unit (GPU) from the perspective of power, computation, and memory. To address this challenge, domain specific specialized digital neural network accelerators based on Field Programmable Gate Array (FPGAs) and Application Specific Integrated Circuits (ASICs) have been developed. However, limitations still exist in terms of on-chip memory capacity, and off-chip memory access. As an alternative, Resistive Random Access Memories (RRAMs), have been proposed to store weights on chip with higher density and enabling fast analog computation with low power consumption. Conductive Bridge Random Access Memories (CBRAMs) is a subset of RRAMs, whose conductance states is defined by the existence and modulation of a conductive metal filament. Ag-Chalcogenide based Conductive Bridge RAM (CBRAM) devices have demonstrated multiple resistive states making them potential candidates for use as analog synapses in neuromorphic hardware. In this work the use of Ag-Ge30Se70 device as an analog synaptic device has been explored. Ag-Ge30Se70 CBRAM crossbar array was fabricated. The fabricated crossbar devices were subjected to different pulsing schemes and conductance linearity response was analyzed. An improved linear response of the devices from a non-linearity factor of 6.65 to 1 for potentiation and -2.25 to -0.95 for depression with non-identical pulse application is observed. The effect of improved linearity was quantified by simulating the devices in an artificial neural network. Simulations for area, latency, and power consumption of the CBRAM device in a neural accelerator was conducted. Further, the changes caused by Total Ionizing Dose (TID) in the conductance of the analog response of Ag-Ge30Se70 Conductive Bridge Random Access Memory (CBRAM)-based synapses are studied. The effect of irradiation was further analyzed by simulating the devices in an artificial neural network. Material characterization was performed to understand the change in conductance observed due to TID.
ContributorsApsangi, Priyanka (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Sanchez Esqueda, Ivan (Committee member) / Marinella, Matthew (Committee member) / Arizona State University (Publisher)
Created2022
Description
This work is aimed at detecting and assessing the performance of colorimetricgold nanoparticle (AuNP) based biosensors, designed to inspect 17-beta-estradiol (E2), SARS-Cov-2 (RBD), and Ebola virus secreted glycoprotein (sGP) with samples at different concentration ranges. The biosensors are able to provide a colorimetric readout, that enables the detection signal to be transmitted via a simple glance, which renders these biosensors cheap and rapid therefore enabling for their implementation into point of care (POC) devices for diagnostic testing in harsh /rural environments, where there is a lack of machinery or trained staff to carry out the diagnosis experiments. Or their implementation into POC devices in medical areas for clinical diagnosis. The intent of this research is to detect the targets of interest such as E2 at a lower limit of detection (LOD), and such as RBD using a novel biosensor design. The verification of the colorimetric results is done via transmission spectra recordings and a compilation of the extinction, where an S-curve relative to the detection concentrations can be seen. This research displays, the fabrication of numerous biosensors and using them in detection experiments to hypothesize the performance of detection using target samples. Additionally, this color change is quantifiable by transmission spectrum recordings to compile the data and calculate the extinction S curve. With the least extinction values pertaining to the highest concentration of detection and the highest extinction values is at the lowest concentration of detection.
ContributorsAltarfa, Mohammad F M M (Author) / Wang, Chao (Thesis advisor) / Kozicki, Michael (Committee member) / Sanchez Esqueda, Ivan (Committee member) / Arizona State University (Publisher)
Created2022
Description
In recent years, the Silicon Super-Junction (SJ) power metal-oxide semiconductor field-effect transistor (MOSFET), has garnered significant interest from spacecraft designers. This is due to their high breakdown voltage and low specific on-state resistance characteristics. Most of the previous research work on power MOSFETS for space applications concentrated on improving the radiation tolerance of low to medium voltage (~ 300V) power MOSFETs. Therefore, understanding and improving the reliability of high voltage SJMOS for the harsh space radiation environment is an important endeavor.In this work, a 600V commercially available silicon planar gate SJMOS is used to study the SJ technology’s tolerance against total ionizing dose (TID) and destructive single event effects (SEE), such as, single event burnout (SEB) and single event gate rupture (SEGR). A technology computer aided design (TCAD) software tool is used to design the SJMOS and simulate its electrical characteristics.
Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide
itride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide
itride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors.
Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance.
Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide
itride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide
itride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors.
Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance.
ContributorsMuthuseenu, Kiraneswar (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Holbert, Keith E. (Committee member) / Gonzalez Velo, Yago (Committee member) / Arizona State University (Publisher)
Created2020
Description
Lateral programmable metallization cells (PMC) utilize the properties of electrodeposits grown over a solid electrolyte channel. Such devices have an active anode and an inert cathode separated by a long electrodeposit channel in a coplanar arrangement. The ability to transport large amount of metallic mass across the channel makes these devices attractive for various More-Than-Moore applications. Existing literature lacks a comprehensive study of electrodeposit growth kinetics in lateral PMCs. Moreover, the morphology of electrodeposit growth in larger, planar devices is also not understood. Despite the variety of applications, lateral PMCs are not embraced by the semiconductor industry due to incompatible materials and high operating voltages needed for such devices. In this work, a numerical model based on the basic processes in PMCs – cation drift and redox reactions – is proposed, and the effect of various materials parameters on the electrodeposit growth kinetics is reported. The morphology of the electrodeposit growth and kinetics of the electrodeposition process are also studied in devices based on Ag-Ge30Se70 materials system. It was observed that the electrodeposition process mainly consists of two regimes of growth – cation drift limited regime and mixed regime. The electrodeposition starts in cation drift limited regime at low electric fields and transitions into mixed regime as the field increases. The onset of mixed regime can be controlled by applied voltage which also affects the morphology of electrodeposit growth. The numerical model was then used to successfully predict the device kinetics and onset of mixed regime. The problem of materials incompatibility with semiconductor manufacturing was solved by proposing a novel device structure. A bilayer structure using semiconductor foundry friendly materials was suggested as a candidate for solid electrolyte. The bilayer structure consists of a low resistivity oxide shunt layer on top of a high resistivity ion carrying oxide layer. Devices using Cu2O as the low resistivity shunt on top of Cu doped WO3 oxide were fabricated. The bilayer devices provided orders of magnitude improvement in device performance in the context of operating voltage and switching time. Electrical and materials characterization revealed the structure of bilayers and the mechanism of electrodeposition in these devices.
ContributorsChamele, Ninad (Author) / Kozicki, Michael (Thesis advisor) / Barnaby, Hugh (Committee member) / Newman, Nathan (Committee member) / Gonzalez-Velo, Yago (Committee member) / Arizona State University (Publisher)
Created2020
Description
With the rapid advancement in the technologies related to renewable energies such
as solar, wind, fuel cell, and many more, there is a definite need for new power con
verting methods involving data-driven methodology. Having adequate information is
crucial for any innovative ideas to fructify; accordingly, moving away from traditional
methodologies is the most practical way of giving birth to new ideas. While working
on a DC-DC buck converter, the input voltages considered for running the simulations
are varied for research purposes. The critical aspect of the new data-driven method
ology is to propose a machine learning algorithm. In this design, solving for inductor
value and power switching losses, the parameters can be achieved while keeping the
input and output ratio close to the value as necessary. Thus, implementing machine
learning algorithms with the traditional design of a non-isolated buck converter deter
mines the optimal outcome for the inductor value and power loss, which is achieved
by assimilating a DC-DC converter and data-driven methodology.
The present thesis investigates the different outcomes from machine learning al
gorithms in comparison with the dynamic equations. Specifically, the DC-DC buck
converter will be focused on the thesis. In order to determine the most effective way
of keeping the system in a steady-state, different circuit buck converter with different
parameters have been performed.
At present, artificial intelligence plays a vital role in power system control and
theory. Consequently, in this thesis, the approximation error estimation has been
analyzed in a DC-DC buck converter model, with specific consideration of machine
learning algorithms tools that can help detect and calculate the difference in terms
of error. These tools, called models, are used to analyze the collected data. In the
present thesis, a focus on such models as K-nearest neighbors (K-NN), specifically
the Weighted-nearest neighbor (WKNN), is utilized for machine learning algorithm
purposes. The machine learning concept introduced in the present thesis lays down
the foundation for future research in this area so that to enable further research on
efficient ways to improve power electronic devices with reduced power switching losses
and optimal inductor values.
as solar, wind, fuel cell, and many more, there is a definite need for new power con
verting methods involving data-driven methodology. Having adequate information is
crucial for any innovative ideas to fructify; accordingly, moving away from traditional
methodologies is the most practical way of giving birth to new ideas. While working
on a DC-DC buck converter, the input voltages considered for running the simulations
are varied for research purposes. The critical aspect of the new data-driven method
ology is to propose a machine learning algorithm. In this design, solving for inductor
value and power switching losses, the parameters can be achieved while keeping the
input and output ratio close to the value as necessary. Thus, implementing machine
learning algorithms with the traditional design of a non-isolated buck converter deter
mines the optimal outcome for the inductor value and power loss, which is achieved
by assimilating a DC-DC converter and data-driven methodology.
The present thesis investigates the different outcomes from machine learning al
gorithms in comparison with the dynamic equations. Specifically, the DC-DC buck
converter will be focused on the thesis. In order to determine the most effective way
of keeping the system in a steady-state, different circuit buck converter with different
parameters have been performed.
At present, artificial intelligence plays a vital role in power system control and
theory. Consequently, in this thesis, the approximation error estimation has been
analyzed in a DC-DC buck converter model, with specific consideration of machine
learning algorithms tools that can help detect and calculate the difference in terms
of error. These tools, called models, are used to analyze the collected data. In the
present thesis, a focus on such models as K-nearest neighbors (K-NN), specifically
the Weighted-nearest neighbor (WKNN), is utilized for machine learning algorithm
purposes. The machine learning concept introduced in the present thesis lays down
the foundation for future research in this area so that to enable further research on
efficient ways to improve power electronic devices with reduced power switching losses
and optimal inductor values.
ContributorsAlsalem, Hamad (Author) / Weng, Yang (Thesis advisor) / Lei, Qin (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2020
Description
Most hardware today is based on von Neumann architecture separating memory from logic. Valuable processing time is lost in shuttling information back and forth between the two units, a problem called von Neumann bottleneck. As transistors are scaled further down, this bottleneck will make it harder to deliver performance in computing power. Adding to this is the increasing complexity of artificial intelligence logic. Thus, there is a need for a faster and more efficient method of computing. Neuromorphic systems deliver this by emulating the massively parallel and fault-tolerant computing capabilities of the human brain where the action potential is triggered by multiple inputs at once (spatial) or an input that builds up over time (temporal). Highly scalable memristors are key in these systems- they can maintain their internal resistive state based on previous current/voltage values thus mimicking the way the strength of two synapses in the brain can vary. The brain-inspired algorithms are implemented by vector matrix multiplications (VMMs) to provide neuronal outputs. High-density conductive bridging random access memory (CBRAM) crossbar arrays (CBAs) can perform VMMs parallelly with ultra-low energy.This research explores a simple planarization technique that could be potentially extended to integrate front-end-of-line (FEOL) processing of complementary metal oxide semiconductor (CMOS) circuitry with back-end-of-line (BEOL) processing of CBRAM CBAs for one-transistor one-resistor (1T1R) Neuromorphic CMOS chips where the transistor is part of the CMOS circuitry and the CBRAM forms the resistor. It is a photoresist (PR) and spin-on glass (SOG) based planarization recipe to planarize CBRAM electrode patterns on a silicon substrate. In this research, however, the planarization is only applied to mechanical grade (MG) silicon wafers without any CMOS layers on them. The planarization achieved was of a very high order (few tens of nanometers). Additionally, the recipe is cost-effective, provides good quality films and simple as only two types of process technologies are involved- lithography and dry etching.
Subsequent processing would involve depositing the CBRAM layers onto the planarized electrodes to form the resistor. Finally, the entire process flow is to be replicated onto wafers with CMOS layers to form the 1T1R circuit.
ContributorsBiswas, Prabaha (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Velo, Yago Gonzalez (Committee member) / Arizona State University (Publisher)
Created2021