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- All Subjects: Electrical Engineering
- Creators: Kitchen, Jennifer
- Creators: Karady, George G.
Description
This thesis addresses the issue of making an economic case for energy storage in power systems. Bulk energy storage has often been suggested for large scale electric power systems in order to levelize load; store energy when it is inexpensive and discharge energy when it is expensive; potentially defer transmission and generation expansion; and provide for generation reserve margins. As renewable energy resource penetration increases, the uncertainty and variability of wind and solar may be alleviated by bulk energy storage technologies. The quadratic programming function in MATLAB is used to simulate an economic dispatch that includes energy storage. A program is created that utilizes quadratic programming to analyze various cases using a 2010 summer peak load from the Arizona transmission system, part of the Western Electricity Coordinating Council (WECC). The MATLAB program is used first to test the Arizona test bed with a low level of energy storage to study how the storage power limit effects several optimization out-puts such as the system wide operating costs. Very high levels of energy storage are then added to see how high level energy storage affects peak shaving, load factor, and other system applications. Finally, various constraint relaxations are made to analyze why the applications tested eventually approach a constant value. This research illustrates the use of energy storage which helps minimize the system wide generator operating cost by "shaving" energy off of the peak demand.
ContributorsRuggiero, John (Author) / Heydt, Gerald T (Thesis advisor) / Datta, Rajib (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis describes the design process used in the creation of a two stage cellular power amplifier. A background for understanding amplifier linearity, device properties, and ACLR estimation is provided. An outline of the design goals is given with a focus on linearity with high efficiency. The full design is broken into smaller elements which are discussed in detail. The main contribution of this thesis is the description of a novel interstage matching network topology for increasing efficiency. Ultimately the full amplifier design is simulated and compared to the measured results and design goals. It was concluded that the design was successful, and used in a commercially available product.
ContributorsSpivey, Erin (Author) / Aberle, James T., 1961- (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Description
The combined heat and power (CHP)-based distributed generation (DG) or dis-tributed energy resources (DERs) are mature options available in the present energy mar-ket, considered to be an effective solution to promote energy efficiency. In the urban en-vironment, the electricity, water and natural gas distribution networks are becoming in-creasingly interconnected with the growing penetration of the CHP-based DG. Subse-quently, this emerging interdependence leads to new topics meriting serious consideration: how much of the CHP-based DG can be accommodated and where to locate these DERs, and given preexisting constraints, how to quantify the mutual impacts on operation performances between these urban energy distribution networks and the CHP-based DG. The early research work was conducted to investigate the feasibility and design methods for one residential microgrid system based on existing electricity, water and gas infrastructures of a residential community, mainly focusing on the economic planning. However, this proposed design method cannot determine the optimal DG sizing and sit-ing for a larger test bed with the given information of energy infrastructures. In this con-text, a more systematic as well as generalized approach should be developed to solve these problems. In the later study, the model architecture that integrates urban electricity, water and gas distribution networks, and the CHP-based DG system was developed. The pro-posed approach addressed the challenge of identifying the optimal sizing and siting of the CHP-based DG on these urban energy networks and the mutual impacts on operation per-formances were also quantified. For this study, the overall objective is to maximize the electrical output and recovered thermal output of the CHP-based DG units. The electrici-ty, gas, and water system models were developed individually and coupled by the devel-oped CHP-based DG system model. The resultant integrated system model is used to constrain the DG's electrical output and recovered thermal output, which are affected by multiple factors and thus analyzed in different case studies. The results indicate that the designed typical gas system is capable of supplying sufficient natural gas for the DG normal operation, while the present water system cannot support the complete recovery of the exhaust heat from the DG units.
ContributorsZhang, Xianjun (Author) / Karady, George G. (Thesis advisor) / Ariaratnam, Samuel T. (Committee member) / Holbert, Keith E. (Committee member) / Si, Jennie (Committee member) / Arizona State University (Publisher)
Created2013
Description
Micro Electro Mechanical Systems (MEMS) is one of the fastest growing field in silicon industry. Low cost production is key for any company to improve their market share. MEMS testing is challenging since input to test a MEMS device require physical stimulus like acceleration, pressure etc. Also, MEMS device vary with process and requires calibration to make them reliable. This increases test cost and testing time. This challenge can be overcome by combining electrical stimulus based testing along with statistical analysis on MEMS response for electrical stimulus and also limited physical stimulus response data. This thesis proposes electrical stimulus based built in self test(BIST) which can be used to get MEMS data and later this data can be used for statistical analysis. A capacitive MEMS accelerometer is considered to test this BIST approach. This BIST circuit overhead is less and utilizes most of the standard readout circuit. This thesis discusses accelerometer response for electrical stimulus and BIST architecture. As a part of this BIST circuit, a second order sigma delta modulator has been designed. This modulator has a sampling frequency of 1MHz and bandwidth of 6KHz. SNDR of 60dB is achieved with 1Vpp differential input signal and 3.3V supply
ContributorsKundur, Vinay (Author) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
Doppler radar can be used to measure respiration and heart rate without contact and through obstacles. In this work, a Doppler radar architecture at 2.4 GHz and a new signal processing algorithm to estimate the respiration and heart rate are presented. The received signal is dominated by the transceiver noise, LO phase noise and clutter which reduces the signal-to-noise ratio of the desired signal. The proposed architecture and algorithm are used to mitigate these issues and obtain an accurate estimate of the heart and respiration rate. Quadrature low-IF transceiver architecture is adopted to resolve null point problem as well as avoid 1/f noise and DC offset due to mixer-LO coupling. Adaptive clutter cancellation algorithm is used to enhance receiver sensitivity coupled with a novel Pattern Search in Noise Subspace (PSNS) algorithm is used to estimate respiration and heart rate. PSNS is a modified MUSIC algorithm which uses the phase noise to enhance Doppler shift detection. A prototype system was implemented using off-the-shelf TI and RFMD transceiver and tests were conduct with eight individuals. The measured results shows accurate estimate of the cardio pulmonary signals in low-SNR conditions and have been tested up to a distance of 6 meters.
ContributorsKhunti, Hitesh Devshi (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Bliss, Daniel (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis work mainly examined the stability and reliability issues of amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors under bias-illumination stress. Amorphous hydrogenated silicon has been the dominating material used in thin film transistors as a channel layer. However with the advent of modern high performance display technologies, it is required to have devices with better current carrying capability and better reproducibility. This brings the idea of new material for channel layer of these devices. Researchers have tried poly silicon materials, organic materials and amorphous mixed oxide materials as a replacement to conventional amorphous silicon layer. Due to its low price and easy manufacturing process, amorphous mixed oxide thin film transistors have become a viable option to replace the conventional ones in order to achieve high performance display circuits. But with new materials emerging, comes the challenge of reliability and stability issues associated with it. Performance measurement under bias stress and bias-illumination stress have been reported previously. This work proposes novel post processing low temperature long time annealing in optimum ambient in order to annihilate or reduce the defects and vacancies associated with amorphous material which lead to the instability or even the failure of the devices. Thin film transistors of a-IGZO has been tested for standalone illumination stress and bias-illumination stress before and after annealing. HP 4155B semiconductor parameter analyzer has been used to stress the devices and measure the output characteristics and transfer characteristics of the devices. Extra attention has been given about the effect of forming gas annealing on a-IGZO thin film. a-IGZO thin film deposited on silicon substrate has been tested for resistivity, mobility and carrier concentration before and after annealing in various ambient. Elastic Recoil Detection has been performed on the films to measure the amount of hydrogen atoms present in the film. Moreover, the circuit parameters of the thin film transistors has been extracted to verify the physical phenomenon responsible for the instability and failure of the devices. Parameters like channel resistance, carrier mobility, power factor has been extracted and variation of these parameters has been observed before and after the stress.
ContributorsRuhul Hasin, Muhammad (Author) / Alford, Terry L. (Thesis advisor) / Krause, Stephen (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
Description
With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This thesis discusses one such block, the sub-ADC (Flash ADC), of the pipeline and sharing it with more than two of the parallel processing channels thereby reducing area and power and input load capacitance to each stage. This work presents a design of 'sub-ADC shared in a time-interleaved pipeline ADC' in the IBM 8HP process. It has been implemented with an offset-compensated, kickback-compensated, fast decision making (large input bandwidth) and low power comparator that forms the core part of the design.
ContributorsBikkina, Phaneendra Kumar (Author) / Barnaby, Hugh (Thesis advisor) / Mikkola, Esko (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
Description
The applications which use MEMS accelerometer have been on rise and many new fields which are using the MEMS devices have been on rise. The industry is trying to reduce the cost of production of these MEMS devices. These devices are manufactured using micromachining and the interface circuitry is manufactured using CMOS and the final product is integrated on to a single chip. Amount spent on testing of the MEMS devices make up a considerable share of the total final cost of the device. In order to save the cost and time spent on testing, researchers have been trying to develop different methodologies. At present, MEMS devices are tested using mechanical stimuli to measure the device parameters and for calibration the device. This testing is necessary since the MEMS process is not a very well controlled process unlike CMOS. This is done using an ATE and the cost of using ATE (automatic testing equipment) contribute to 30-40% of the devices final cost. This thesis proposes an architecture which can use an Electrical Signal to stimulate the MEMS device and use the data from the MEMS response in approximating the calibration coefficients efficiently. As a proof of concept, we have designed a BIST (Built-in self-test) circuit for MEMS accelerometer. The BIST has an electrical stimulus generator, Capacitance-to-voltage converter, ∑ ∆ ADC. This thesis explains in detail the design of the Electrical stimulus generator. We have also designed a technique to correlate the parameters obtained from electrical stimuli to those obtained by mechanical stimuli. This method is cost effective since the additional circuitry needed to implement BIST is less since the technique utilizes most of the existing standard readout circuitry already present.
ContributorsJangala Naga, Naveen Sai (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
Description
The future grid will face challenges to meet an increased power demand by the consumers. Various solutions were studied to address this issue. One alternative to realize increased power flow in the grid is to use High Temperature Low Sag (HTLS) since it fulfills essential criteria of less sag and good material performance with temperature. HTLS conductors like Aluminum Conductor Composite Reinforced (ACCR) and Aluminum Conductor Carbon Composite (ACCC) are expected to face high operating temperatures of 150-200 degree Celsius in order to achieve the desired increased power flow. Therefore, it is imperative to characterize the material performance of these conductors with temperature. The work presented in this thesis addresses the characterization of carbon composite core based and metal matrix core based HTLS conductors. The thesis focuses on the study of variation of tensile strength of the carbon composite core with temperature and the level of temperature rise of the HTLS conductors due to fault currents cleared by backup protection. In this thesis, Dynamic Mechanical Analysis (DMA) was used to quantify the loss in storage modulus of carbon composite cores with temperature. It has been previously shown in literature that storage modulus is correlated to the tensile strength of the composite. Current temperature relationships of HTLS conductors were determined using the IEEE 738-2006 standard. Temperature rise of these conductors due to fault currents were also simulated. All simulations were performed using Microsoft Visual C++ suite. Tensile testing of metal matrix core was also performed. Results of DMA on carbon composite cores show that the storage modulus, hence tensile strength, decreases rapidly in the temperature range of intended use. DMA on composite cores subjected to heat treatment were conducted to investigate any changes in the variation of storage modulus curves. The experiments also indicates that carbon composites cores subjected to temperatures at or above 250 degree Celsius can cause permanent loss of mechanical properties including tensile strength. The fault current temperature analysis of carbon composite based conductors reveal that fault currents eventually cleared by backup protection in the event of primary protection failure can cause damage to fiber matrix interface.
ContributorsBanerjee, Koustubh (Author) / Gorur, Ravi (Committee member) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2014
Description
In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time.
ContributorsKim, Kibeom (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2013