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- All Subjects: Electrical Engineering
- Creators: Kitchen, Jennifer
- Creators: Karady, George G.
- Creators: Ogras, Umit Y.
Description
The development of a Solid State Transformer (SST) that incorporates a DC-DC multiport converter to integrate both photovoltaic (PV) power generation and battery energy storage is presented in this dissertation. The DC-DC stage is based on a quad-active-bridge (QAB) converter which not only provides isolation for the load, but also for the PV and storage. The AC-DC stage is implemented with a pulse-width-modulated (PWM) single phase rectifier. A unified gyrator-based average model is developed for a general multi-active-bridge (MAB) converter controlled through phase-shift modulation (PSM). Expressions to determine the power rating of the MAB ports are also derived. The developed gyrator-based average model is applied to the QAB converter for faster simulations of the proposed SST during the control design process as well for deriving the state-space representation of the plant. Both linear quadratic regulator (LQR) and single-input-single-output (SISO) types of controllers are designed for the DC-DC stage. A novel technique that complements the SISO controller by taking into account the cross-coupling characteristics of the QAB converter is also presented herein. Cascaded SISO controllers are designed for the AC-DC stage. The QAB demanded power is calculated at the QAB controls and then fed into the rectifier controls in order to minimize the effect of the interaction between the two SST stages. The dynamic performance of the designed control loops based on the proposed control strategies are verified through extensive simulation of the SST average and switching models. The experimental results presented herein show that the transient responses for each control strategy match those from the simulations results thus validating them.
ContributorsFalcones, Sixifo Daniel (Author) / Ayyanar, Raja (Thesis advisor) / Karady, George G. (Committee member) / Tylavsky, Daniel (Committee member) / Tsakalis, Konstantinos (Committee member) / Arizona State University (Publisher)
Created2011
Description
This research work describes the design of a fault current limiter (FCL) using digital logic and a microcontroller based data acquisition system for an ultra fast pilot protection system. These systems have been designed according to the requirements of the Future Renewable Electric Energy Delivery and Management (FREEDM) system (or loop), a 1 MW green energy hub. The FREEDM loop merges advanced power electronics technology with information tech-nology to form an efficient power grid that can be integrated with the existing power system. With the addition of loads to the FREEDM system, the level of fault current rises because of increased energy flow to supply the loads, and this requires the design of a limiter which can limit this current to a level which the existing switchgear can interrupt. The FCL limits the fault current to around three times the rated current. Fast switching Insulated-gate bipolar transistor (IGBT) with its gate control logic implements a switching strategy which enables this operation. A complete simulation of the system was built on Simulink and it was verified that the FCL limits the fault current to 1000 A compared to more than 3000 A fault current in the non-existence of a FCL. This setting is made user-defined. In FREEDM system, there is a need to interrupt a fault faster or make intelligent deci-sions relating to fault events, to ensure maximum availability of power to the loads connected to the system. This necessitates fast acquisition of data which is performed by the designed data acquisition system. The microcontroller acquires the data from a current transformer (CT). Mea-surements are made at different points in the FREEDM system and merged together, to input it to the intelligent protection algorithm that has been developed by another student on the project. The algorithm will generate a tripping signal in the event of a fault. The developed hardware and the programmed software to accomplish data acquisition and transmission are presented here. The designed FCL ensures that the existing switchgear equipments need not be replaced thus aiding future power system expansion. The developed data acquisition system enables fast fault sensing in protection schemes improving its reliability.
ContributorsThirumalai, Arvind (Author) / Karady, George G. (Thesis advisor) / Vittal, Vijay (Committee member) / Hedman, Kory (Committee member) / Arizona State University (Publisher)
Created2011
Description
All-dielectric self-supporting (ADSS) fiber optic cables are used for data transfer by the utilities. They are installed along high voltage transmission lines. Dry band arcing, a phenomenon which is observed in outdoor insulators, is also observed in ADSS cables. The heat developed during dry band arcing damages the ADSS cables' outer sheath. A method is presented here to rate the cable sheath using the power developed during dry band arcing. Because of the small diameter of ADSS cables, mechanical vibration is induced in ADSS cable. In order to avoid damage, vibration dampers known as spiral vibration dampers (SVD) are used over these ADSS cables. These dampers are installed near the armor rods, where the presence of leakage current and dry band activity is more. The effect of dampers on dry band activity is investigated by conducting experiments on ADSS cable and dampers. Observations made from the experiments suggest that the hydrophobicity of the cable and damper play a key role in stabilizing dry band arcs. Hydrophobic-ity of the samples have been compared. The importance of hydrophobicity of the samples is further illustrated with the help of simulation results. The results indi-cate that the electric field increases at the edges of water strip. The dry band arc-ing phenomenon could thus be correlated to the hydrophobicity of the outer sur-face of cable and damper.
ContributorsPrabakar, Kumaraguru (Author) / Karady, George G. (Thesis advisor) / Vittal, Vijay (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
Description
An embedded HVDC system is a dc link with at least two ends being physically connected within a single synchronous ac network. The thesis reviews previous works on embedded HVDC, proposes a dynamic embedded HVDC model by PSCAD program, and compares the transient stability performance among AC, DC and embedded HVDC. The test results indicate that by installing the embedded HVDC, AC network transient stability performance has been largely improved. Therefore the thesis designs a novel frequency control topology for embedded HVDC. According to the dynamic performance test results, when the embedded HVDC system equipped with a frequency control, the system transient stability will be improved further.
ContributorsYu, Jicheng (Author) / Karady, George G. (Thesis advisor) / Hui, Yu (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2013
Description
This dissertation presents a new hybrid fault current limiter (FCL) topology that is primarily intended to protect single-phase power equipment. It can however be extended to protect three phase systems but would need three devices to protect each individual phase. In comparison against the existing fault current limiter technology, the salient fea-tures of the proposed topology are: a) provides variable impedance that provides a 50% reduction in prospective fault current; b) near instantaneous response time which is with-in the first half cycle (1-4 ms); c) the use of semiconductor switches as the commutating switch which produces reduced leakage current, reduced losses, improved reliability, and a faster switch time (ns-µs); d) zero losses in steady-state operation; e) use of a Neodym-ium (NdFeB) permanent magnet as the limiting impedance which reduces size, cost, weight, eliminates DC biasing and cooling costs; f) use of Pulse Width Modulation (PWM) to control the magnitude of the fault current to a user's desired level. g) experi-mental test system is developed and tested to prove the concepts of the proposed FCL. This dissertation presents the proposed topology and its working principle backed up with numerical verifications, simulation results, and hardware implementation results. Conclu-sions and future work are also presented.
ContributorsPrigmore, Jay (Author) / Karady, George G. (Thesis advisor) / Ayyanar, Raja (Committee member) / Holbert, Keith E. (Committee member) / Hedman, Kory (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis presents an overview of the calculation and application of locational marginal prices in electric power systems particularly pertaining to the distribution system. The terminology proposed is a distribution locational marginal price or DLMP. The calculation of locational process in distribution engineering is conjectured and discussed. The use of quadratic programming for this calculation is proposed and illustrated. A small four bus test bed exemplifies the concept and then the concept is expanded to the IEEE 34 bus distribution system. Alternatives for the calculation are presented, and approximations are reviewed. Active power losses in the system are modeled and incorporated by two different methods. These calculation methods are also applied to the 34 bus system. The results from each method are compared to results found using the PowerWorld simulator. The application of energy management using the DLMP to control load is analyzed as well. This analysis entails the use of the DLMP to cause certain controllable loads to decrease when the DLMP is high, and vice-versa. Tests are done to illustrate the impact of energy management using DLMPs for residential, commercial, and industrial controllable loads. Results showing the dynamics of the loads are shown. The use and characteristics of Matlab function FMINCON are presented in an appendix.
ContributorsSteffan, Nick (Author) / Heydt, Gerald T (Thesis advisor) / Hedman, Kory (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis concerns the flashover issue of the substation insulators operating in a polluted environment. The outdoor insulation equipment used in the power delivery infrastructure encounter different types of pollutants due to varied environmental conditions. Various methods have been developed by manufacturers and researchers to mitigate the flashover problem. The application of Room Temperature Vulcanized (RTV) silicone rubber is one such favorable method as it can be applied over the already installed units. Field experience has already showed that the RTV silicone rubber coated insulators have a lower flashover probability than the uncoated insulators. The scope of this research is to quantify the improvement in the flashover performance. Artificial contamination tests were carried on station post insulators for assessing their performance. A factorial experiment design was used to model the flashover performance. The formulation included the severity of contamination and leakage distance of the insulator samples. Regression analysis was used to develop a mathematical model from the data obtained from the experiments. The main conclusion drawn from the study is that the RTV coated insulators withstood much higher levels of contamination even when the coating had lost its hydrophobicity. This improvement in flashover performance was found to be in the range of 20-40%. A much better flashover performance was observed when the coating recovered its hydrophobicity. It was also seen that the adhesion of coating was excellent even after many tests which involved substantial discharge activity.
ContributorsGholap, Vipul (Author) / Gorur, Ravi S (Thesis advisor) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2013
Description
Radio frequency (RF) transceivers require a disproportionately high effort in terms of test development time, test equipment cost, and test time. The relatively high test cost stems from two contributing factors. First, RF transceivers require the measurement of a diverse set of specifications, requiring multiple test set-ups and long test times, which complicates load-board design, debug, and diagnosis. Second, high frequency operation necessitates the use of expensive equipment, resulting in higher per second test time cost compared with mixed-signal or digital circuits. Moreover, in terms of the non-recurring engineering cost, the need to measure complex specfications complicates the test development process and necessitates a long learning process for test engineers. Test time is dominated by changing and settling time for each test set-up. Thus, single set-up test solutions are desirable. Loop-back configuration where the transmitter output is connected to the receiver input are used as the desirable test set- up for RF transceivers, since it eliminates the reliance on expensive instrumentation for RF signal analysis and enables measuring multiple parameters at once. In-phase and Quadrature (IQ) imbalance, non-linearity, DC offset and IQ time skews are some of the most detrimental imperfections in transceiver performance. Measurement of these parameters in the loop-back mode is challenging due to the coupling between the receiver (RX) and transmitter (TX) parameters. Loop-back based solutions are proposed in this work to resolve this issue. A calibration algorithm for a subset of the above mentioned impairments is also presented. Error Vector Magnitude (EVM) is a system-level parameter that is specified for most advanced communication standards. EVM measurement often takes extensive test development efforts, tester resources, and long test times. EVM is analytically related to system impairments, which are typically measured in a production test i environment. Thus, EVM test can be eliminated from the test list if the relations between EVM and system impairments are derived independent of the circuit implementation and manufacturing process. In this work, the focus is on the WLAN standard, and deriving the relations between EVM and three of the most detrimental impairments for QAM/OFDM based systems (IQ imbalance, non-linearity, and noise). Having low cost test techniques for measuring the RF transceivers imperfections and being able to analytically compute EVM from the measured parameters is a complete test solution for RF transceivers. These techniques along with the proposed calibration method can be used in improving the yield by widening the pass/fail boundaries for transceivers imperfections. For all of the proposed methods, simulation and hardware measurements prove that the proposed techniques provide accurate characterization of RF transceivers.
ContributorsNassery, Afsaneh (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
Description
Underground cables have been widely used in big cities. This is because underground cables offer the benefits of reducing visual impact and the disturbance caused by bad weather (wind, ice, snow, and the lightning strikes). Additionally, when placing power lines underground, the maintenance costs can also be reduced as a result. The underground cable rating calculation is the most critical part of designing the cable construction and cable installation. In this thesis, three contributions regarding the cable ampacity study have been made. First, an analytical method for rating of underground cables has been presented. Second, this research also develops the steady state and transient ratings for Salt River Project (SRP) 69 kV underground system using the commercial software CYMCAP for several typical substations. Third, to find an alternative way to predict the cable ratings, three regression models have been built. The residual plot and mean square error for the three methods have been analyzed. The conclusion is dawn that the nonlinear regression model provides the sufficient accuracy of the cable rating prediction for SRP's typical installation.
ContributorsWang, Tong (Author) / Tylavsky, Daniel (Thesis advisor) / Karady, George G. (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2013
Description
Synchronous buck converters have become the obvious choice of design for high efficiency voltage down-conversion applications and find wide scale usage in today's IC industry. The use of digital control in synchronous buck converters is becoming increasingly popular because of its associated advantages over traditional analog counterparts in terms of design flexibility, reduced use of off-chip components, and better programmability to enable advanced controls. They also demonstrate better immunity to noise, enhances tolerance to the process, voltage and temperature (PVT) variations, low chip area and as a result low cost. It enables processing in digital domain requiring a need of analog-digital interfacing circuit viz. Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC). A Digital to Pulse Width Modulator (DPWM) acts as time domain DAC required in the control loop to modulate the ON time of the Power-MOSFETs. The accuracy and efficiency of the DPWM creates the upper limit to the steady state voltage ripple of the DC - DC converter and efficiency in low load conditions. This thesis discusses the prevalent architectures for DPWM in switched mode DC - DC converters. The design of a Hybrid DPWM is presented. The DPWM is 9-bit accurate and is targeted for a Synchronous Buck Converter with a switching frequency of 1.0 MHz. The design supports low power mode(s) for the buck converter in the Pulse Frequency Modulation (PFM) mode as well as other fail-safe features. The design implementation is digital centric making it robust across PVT variations and portable to lower technology nodes. Key target of the design is to reduce design time. The design is tested across large Process (+/- 3σ), Voltage (1.8V +/- 10%) and Temperature (-55.0 °C to 125 °C) and is in the process of tape-out.
ContributorsKumar, Amit (Author) / Bakkaloglu, Bertan (Thesis advisor) / Song, Hongjiang (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013