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- All Subjects: Electrical Engineering
- Genre: Doctoral Dissertation
- Creators: Yu, Hongbin
Description
A workload-aware low-power neuromorphic controller for dynamic power and thermal management in VLSI systems is presented. The neuromorphic controller predicts future workload and temperature values based on the past values and CPU performance counters and preemptively regulates supply voltage and frequency. System-level measurements from stateof-the-art commercial microprocessors are used to get workload, temperature and CPU performance counter values. The controller is designed and simulated using circuit-design and synthesis tools. At device-level, on-chip planar inductors suffer from low inductance occupying large chip area. On-chip inductors with integrated magnetic materials are designed, simulated and fabricated to explore performance-efficiency trade offs and explore potential applications such as resonant clocking and on-chip voltage regulation. A system level study is conducted to evaluate the effect of on-chip voltage regulator employing magnetic inductors as the output filter. It is concluded that neuromorphic power controller is beneficial for fine-grained per-core power management in conjunction with on-chip voltage regulators utilizing scaled magnetic inductors.
ContributorsSinha, Saurabh (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Yu, Hongbin (Committee member) / Christen, Jennifer B. (Committee member) / Arizona State University (Publisher)
Created2011
Description
CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to the continual scaling of CMOS devices. In this work the three primary intrinsic variations sources are studied, including random dopant fluctuation (RDF), line-edge roughness (LER) and oxide thickness fluctuation (OTF). The research is focused on the modeling and simulation of those variations and their scaling trends. Besides the three variations, a time dependent variation source, Random Telegraph Noise (RTN) is also studied. Different from the other three variations, RTN does not contribute much to the total variation amount, but aggregate the worst case of Vth variations in CMOS. In this work a TCAD based simulation study on RTN is presented, and a new SPICE based simulation method for RTN is proposed for time domain circuit analysis. Process-induced variations arise from the imperfection in silicon fabrication, and vary from foundries to foundries. In this work the layout dependent Vth shift due to Rapid-Thermal Annealing (RTA) are investigated. In this work, we develop joint thermal/TCAD simulation and compact modeling tools to analyze performance variability under various layout pattern densities and RTA conditions. Moreover, we propose a suite of compact models that bridge the underlying RTA process with device parameter change for efficient design optimization.
ContributorsYe, Yun, Ph.D (Author) / Cao, Yu (Thesis advisor) / Yu, Hongbin (Committee member) / Song, Hongjiang (Committee member) / Clark, Lawrence (Committee member) / Arizona State University (Publisher)
Created2011
Description
With increasing demand for System on Chip (SoC) and System in Package (SiP) design in computer and communication technologies, integrated inductor which is an essential passive component has been widely used in numerous integrated circuits (ICs) such as in voltage regulators and RF circuits. In this work, soft ferromagnetic core material, amorphous Co-Zr-Ta-B, was incorporated into on-chip and in-package inductors in order to scale down inductors and improve inductors performance in both inductance density and quality factor. With two layers of 500 nm Co-Zr-Ta-B films a 3.5X increase in inductance and a 3.9X increase in quality factor over inductors without magnetic films were measured at frequencies as high as 1 GHz. By laminating technology, up to 9.1X increase in inductance and more than 5X increase in quality factor (Q) were obtained from stripline inductors incorporated with 50 nm by 10 laminated films with a peak Q at 300 MHz. It was also demonstrated that this peak Q can be pushed towards high frequency as far as 1GHz by a combination of patterning magnetic films into fine bars and laminations. The role of magnetic vias in magnetic flux and eddy current control was investigated by both simulation and experiment using different patterning techniques and by altering the magnetic via width. Finger-shaped magnetic vias were designed and integrated into on-chip RF inductors improving the frequency of peak quality factor from 400 MHz to 800 MHz without sacrificing inductance enhancement. Eddy current and magnetic flux density in different areas of magnetic vias were analyzed by HFSS 3D EM simulation. With optimized magnetic vias, high frequency response of up to 2 GHz was achieved. Furthermore, the effect of applied magnetic field on on-chip inductors was investigated for high power applications. It was observed that as applied magnetic field along the hard axis (HA) increases, inductance maintains similar value initially at low fields, but decreases at larger fields until the magnetic films become saturated. The high frequency quality factor showed an opposite trend which is correlated to the reduction of ferromagnetic resonant absorption in the magnetic film. In addition, experiments showed that this field-dependent inductance change varied with different patterned magnetic film structures, including bars/slots and fingers structures. Magnetic properties of Co-Zr-Ta-B films on standard organic package substrates including ABF and polyimide were also characterized. Effects of substrate roughness and stress were analyzed and simulated which provide strategies for integrating Co-Zr-Ta-B into package inductors and improving inductors performance. Stripline and spiral inductors with Co-Zr-Ta-B films were fabricated on both ABF and polyimide substrates. Maximum 90% inductance increase in hundreds MHz frequency range were achieved in stripline inductors which are suitable for power delivery applications. Spiral inductors with Co-Zr-Ta-B films showed 18% inductance increase with quality factor of 4 at frequency up to 3 GHz.
ContributorsWu, Hao (Author) / Yu, Hongbin (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Chickamenahalli, Shamala (Committee member) / Arizona State University (Publisher)
Created2013
Description
Zinc oxide (ZnO), a naturally n-type semiconductor has been identified as a promising candidate to replace indium tin oxide (ITO) as the transparent electrode in solar cells, because of its wide bandgap (3.37 eV), abundant source materials and suitable refractive index (2.0 at 600 nm). Spray deposition is a convenient and low cost technique for large area and uniform deposition of semiconductor thin films. In particular, it provides an easier way to dope the film by simply adding the dopant precursor into the starting solution. In order to reduce the resistivity of undoped ZnO, many works have been done by doping in the ZnO with either group IIIA elements or VIIA elements using spray pyrolysis. However, the resistivity is still too high to meet TCO's resistivity requirement. In the present work, a novel co-spray deposition technique is developed to bypass a fundamental limitation in the conventional spray deposition technique, i.e. the deposition of metal oxides from incompatible precursors in the starting solution. With this technique, ZnO films codoped with one cationic dopant, Al, Cr, or Fe, and an anionic dopant, F, have been successfully synthesized, in which F is incompatible with all these three cationic dopants. Two starting solutions were prepared and co-sprayed through two separate spray heads. One solution contained only the F precursor, NH 4F. The second solution contained the Zn and one cationic dopant precursors, Zn(O 2CCH 3) 2 and AlCl 3, CrCl 3, or FeCl 3. The deposition was carried out at 500 °C; on soda-lime glass in air. Compared to singly-doped ZnO thin films, codoped ZnO samples showed better electrical properties. Besides, a minimum sheet resistance, 55.4 Ω/sq, was obtained for Al and F codoped ZnO films after vacuum annealing at 400 °C;, which was lower than singly-doped ZnO with either Al or F. The transmittance for the Al and F codoped ZnO samples was above 90% in the visible range. This co-spray deposition technique provides a simple and cost-effective way to synthesize metal oxides from incompatible precursors with improved properties.
ContributorsZhou, Bin (Author) / Tao, Meng (Thesis advisor) / Goryll, Michael (Committee member) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2013
Description
Characterization of standard cells is one of the crucial steps in the IC design. Scaling of CMOS technology has lead to timing un-certainties such as that of cross coupling noise due to interconnect parasitic, skew variation due to voltage jitter and proximity effect of multiple inputs switching (MIS). Due to increased operating frequency and process variation, the probability of MIS occurrence and setup / hold failure within a clock cycle is high. The delay variation due to temporal proximity of MIS is significant for multiple input gates in the standard cell library. The shortest paths are affected by MIS due to the lack of averaging effect. Thus, sensitive designs such as that of SRAM row and column decoder circuits have high probability for MIS impact. The traditional static timing analysis (STA) assumes single input switching (SIS) scenario which is not adequate enough to capture gate delay accurately, as the delay variation due to temporal proximity of the MIS is ~15%-45%. Whereas, considering all possible scenarios of MIS for characterization is computationally intensive with huge data volume. Various modeling techniques are developed for the characterization of MIS effect. Some techniques require coefficient extraction through multiple spice simulation, and do not discuss speed up approach or apply models with complicated algorithms to account for MIS effect. The STA flow accounts for process variation through uncertainty parameter to improve product yield. Some of the MIS delay variability models account for MIS variation through table look up approach, resulting in huge data volume or do not consider propagation of RAT in the design flow. Thus, there is a need for a methodology to model MIS effect with less computational resource, and integration of such effect into design flow without trading off the accuracy. A finite-point based analytical model for MIS effect is proposed for multiple input logic gates and similar approach is extended for setup/hold characterization of sequential elements. Integration of MIS variation into design flow is explored. The proposed methodology is validated using benchmark circuits at 45nm technology node under process variation. Experimental results show significant reduction in runtime and data volume with ~10% error compared to that of SPICE simulation.
ContributorsSubramaniam, Anupama R (Author) / Cao, Yu (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Roveda, Janet (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
This thesis summarizes the research work carried out on design, modeling and simulation of semiconductor nanophotonic devices. The research includes design of nanowire (NW) lasers, modeling of active plasmonic waveguides, design of plasmonic nano-lasers, and design of all-semiconductor plasmonic systems. For the NW part, a comparative study of electrical injection in the longitudinal p-i-n and coaxial p-n core-shell NWs was performed. It is found that high density carriers can be efficiently injected into and confined in the core-shell structure. The required bias voltage and doping concentrations in the core-shell structure are smaller than those in the longitudinal p-i-n structure. A new device structure with core-shell configuration at the p and n contact regions for electrically driven single NW laser was proposed. Through a comprehensive design trade-off between threshold gain and threshold voltage, room temperature lasing has been proved in the laser with low threshold current and large output efficiency. For the plasmonic part, the propagation of surface plasmon polariton (SPP) in a metal-semiconductor-metal structure where semiconductor is highly excited to have an optical gain was investigated. It is shown that near the resonance the SPP mode experiences an unexpected giant modal gain that is 1000 times of the material gain in the semiconductor and the corresponding confinement factor is as high as 105. The physical origin of the giant modal gain is the slowing down of the average energy propagation in the structure. Secondly, SPP modes lasing in a metal-insulator-semiconductor multi-layer structure was investigated. It is shown that the lasing threshold can be reduced by structural optimization. A specific design example was optimized using AlGaAs/GaAs/AlGaAs single quantum well sandwiched between silver layers. This cavity has a physical volume of 1.5×10-4 λ03 which is the smallest nanolaser reported so far. Finally, the all-semiconductor based plasmonics was studied. It is found that InAs is superior to other common semiconductors for plasmonic application in mid-infrared range. A plasmonic system made of InAs, GaSb and AlSb layers, consisting of a plasmonic source, waveguide and detector was proposed. This on-chip integrated system is realizable in a single epitaxial growth process.
ContributorsLi, Debin (Author) / Ning, Cun-Zheng (Thesis advisor) / Zhang, Yong-Hang (Committee member) / Balanis, Constantine A (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
In today's world there is a great need for sensing methods as tools to provide critical information to solve today's problems in security applications. Real time detection of trace chemicals, such as explosives, in a complex environment containing various interferents using a portable device that can be reliably deployed in a field has been a difficult challenge. A hybrid nanosensor based on the electrochemical reduction of trinitrotoluene (TNT) and the interaction of the reduction products with conducting polymer nanojunctions in an ionic liquid was fabricated. The sensor simultaneously measures the electrochemical current from the reduction of TNT and the conductance change of the polymer nanojunction caused from the reduction product. The hybrid detection mechanism, together with the unique selective preconcentration capability of the ionic liquid, provides a selective, fast, and sensitive detection of TNT. The sensor, in its current form, is capable of detecting parts per trillion level TNT in the presence of various interferents within a few minutes. A novel hybrid electrochemical-colorimetric (EC-C) sensing platform was also designed and fabricated to meet these challenges. The hybrid sensor is based on electrochemical reactions of trace explosives, colorimetric detection of the reaction products, and unique properties of the explosives in an ionic liquid (IL). This approach affords not only increased sensitivity but also selectivity as evident from the demonstrated null rate of false positives and low detection limits. Using an inexpensive webcam a detection limit of part per billion in volume (ppbV) has been achieved and demonstrated selective detection of explosives in the presence of common interferences (perfumes, mouth wash, cleaners, petroleum products, etc.). The works presented in this dissertation, were published in the Journal of the American Chemical Society (JACS, 2009) and Nano Letters (2010), won first place in the National Defense Research contest in (2009) and has been granted a patent (WO 2010/030874 A1). In addition, other work related to conductive polymer junctions and their sensing capabilities has been published in Applied Physics Letters (2005) and IEEE sensors journal (2008).
ContributorsDiaz Aguilar, Alvaro (Author) / Tao, Nongjian (Thesis advisor) / Tsui, Raymond (Committee member) / Barnaby, Hugh (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
Studying charge transport through single molecules tethered between two metal electrodes is of fundamental importance in molecular electronics. Over the years, a variety of methods have been developed in attempts of performing such measurements. However, the limitation of these techniques is still one of the factors that prohibit one from gaining a thorough understanding of single molecule junctions. Firstly, the time resolution of experiments is typically limited to milli to microseconds, while molecular dynamics simulations are carried out on the time scale of pico to nanoseconds. A huge gap therefore persists between the theory and the experiments. This thesis demonstrates a nanosecond scale measurement of the gold atomic contact breakdown process. A combined setup of DC and AC circuits is employed, where the AC circuit reveals interesting observations in nanosecond scale not previously seen using conventional DC circuits. The breakdown time of gold atomic contacts is determined to be faster than 0.1 ns and subtle atomic events are observed within nanoseconds. Furthermore, a new method based on the scanning tunneling microscope break junction (STM-BJ) technique is developed to rapidly record thousands of I-V curves from repeatedly formed single molecule junctions. 2-dimensional I-V and conductance-voltage (G-V) histograms constructed using the acquired data allow for more meaningful statistical analysis to single molecule I-V characteristics. The bias voltage adds an additional dimension to the conventional single molecule conductance measurement. This method also allows one to perform transition voltage spectra (TVS) for individual junctions and to study the correlation between the conductance and the tunneling barrier height. The variation of measured conductance values is found to be primarily determined by the poorly defined contact geometry between the molecule and metal electrodes, rather than the tunnel barrier height. In addition, the rapid I-V technique is also found useful in studying thermoelectric effect in single molecule junctions. When applying a temperature gradient between the STM tip and substrate in air, the offset current at zero bias in the I-V characteristics is a measure of thermoelectric current. The rapid I-V technique allows for statistical analysis of such offset current at different temperature gradients and thus the Seebeck coefficient of single molecule junctions is measured. Combining with single molecule TVS, the Seebeck coefficient is also found to be a measure of tunnel barrier height.
ContributorsGuo, Shaoyin (Author) / Tao, Nongjian (Thesis advisor) / Bennett, Peter (Committee member) / Ning, Cun-Zheng (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
What can classical chaos do to quantum systems is a fundamental issue highly relevant to a number of branches in physics. The field of quantum chaos has been active for three decades, where the focus was on non-relativistic quantumsystems described by the Schr¨odinger equation. By developing an efficient method to solve the Dirac equation in the setting where relativistic particles can tunnel between two symmetric cavities through a potential barrier, chaotic cavities are found to suppress the spread in the tunneling rate. Tunneling rate for any given energy assumes a wide range that increases with the energy for integrable classical dynamics. However, for chaotic underlying dynamics, the spread is greatly reduced. A remarkable feature, which is a consequence of Klein tunneling, arise only in relativistc quantum systems that substantial tunneling exists even for particle energy approaching zero. Similar results are found in graphene tunneling devices, implying high relevance of relativistic quantum chaos to the development of such devices. Wave propagation through random media occurs in many physical systems, where interesting phenomena such as branched, fracal-like wave patterns can arise. The generic origin of these wave structures is currently a matter of active debate. It is of fundamental interest to develop a minimal, paradigmaticmodel that can generate robust branched wave structures. In so doing, a general observation in all situations where branched structures emerge is non-Gaussian statistics of wave intensity with an algebraic tail in the probability density function. Thus, a universal algebraic wave-intensity distribution becomes the criterion for the validity of any minimal model of branched wave patterns. Coexistence of competing species in spatially extended ecosystems is key to biodiversity in nature. Understanding the dynamical mechanisms of coexistence is a fundamental problem of continuous interest not only in evolutionary biology but also in nonlinear science. A continuous model is proposed for cyclically competing species and the effect of the interplay between the interaction range and mobility on coexistence is investigated. A transition from coexistence to extinction is uncovered with a non-monotonic behavior in the coexistence probability and switches between spiral and plane-wave patterns arise. Strong mobility can either promote or hamper coexistence, while absent in lattice-based models, can be explained in terms of nonlinear partial differential equations.
ContributorsNi, Xuan (Author) / Lai, Ying-Cheng (Thesis advisor) / Huang, Liang (Committee member) / Yu, Hongbin (Committee member) / Akis, Richard (Committee member) / Arizona State University (Publisher)
Created2012
Description
Negative bias temperature instability (NBTI) is a leading aging mechanism in modern digital and analog circuits. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and Dynamic Voltage Scaling (DVS) in real circuit operation. To overcome these barriers, the modeling effort in this work (1) practically explains the aging statistics due to randomness in number of traps with log(t) model, accurately predicting the mean and variance shift; (2) proposes cycle-to-cycle model (from the first-principle of trapping) to handle aging under multiple supply voltages, predicting the non-monotonic behavior under DVS (3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles, and (4) comprehensively validates the new set of aging models with 65nm statistical silicon data. Compared to previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard-banding during the design stage. With CMOS technology scaling, design for reliability has become an important step in the design cycle, and increased the need for efficient and accurate aging simulation methods during the design stage. NBTI induced delay shifts in logic paths are asymmetric in nature, as opposed to averaging effect due to recovery assumed in traditional aging analysis. Timing violations due to aging, in particular, are very sensitive to the standby operation regime of a digital circuit. In this report, by identifying the critical moments in circuit operation and considering the asymmetric aging effects, timing violations under NBTI effect are correctly predicted. The unique contributions of the simulation flow include: (1) accurate modeling of aging induced delay shift due to threshold voltage (Vth) shift using only the delay dependence on supply voltage from cell library; (2) simulation flow for asymmetric aging analysis is proposed and conducted at critical points in circuit operation; (3) setup and hold timing violations due to NBTI aging in logic and clock buffer are investigated in sequential circuits and (4) proposed framework is tested in VLSI applications such DDR memory circuits. This methodology is comprehensively demonstrated with ISCAS89 benchmark circuits using a 45nm Nangate standard cell library characterized using predictive technology models. Our proposed design margin assessment provides design insights and enables resilient techniques for mitigating digital circuit aging.
ContributorsVelamala, Jyothi Bhaskarr (Author) / Cao, Yu (Thesis advisor) / Clark, Lawrence (Committee member) / Chakrabarti, Chaitali (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012