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Description
There is a pervasive need in the defense industry for conformal, low-profile, efficient and broadband (HF-UHF) antennas. Broadband capabilities enable shared aperture multi-function radiators, while conformal antenna profiles minimize physical damage in army applications, reduce drag and weight penalties in airborne applications and reduce the visual and RF signatures of the communication node. This dissertation is concerned with a new class of antennas called Magneto-Dielectric wire antennas (MDWA) that provide an ideal solution to this ever-present and growing need. Magneto-dielectric structures (μr>1;εr>1) can partially guide electromagnetic waves and radiate them by leaking off the structure or by scattering from any discontinuities, much like a metal antenna of the same shape. They are attractive alternatives to conventional whip and blade antennas because they can be placed conformal to a metallic ground plane without any performance penalty. A two pronged approach is taken to analyze MDWAs. In the first, antenna circuit models are derived for the prototypical dipole and loop elements that include the effects of realistic dispersive magneto-dielectric materials of construction. A material selection law results, showing that: (a) The maximum attainable efficiency is determined by a single magnetic material parameter that we term the hesitivity: Closely related to Snoek's product, it measures the maximum magnetic conductivity of the material. (b) The maximum bandwidth is obtained by placing the highest amount of μ" loss in the frequency range of operation. As a result, high radiation efficiency antennas can be obtained not only from the conventional low loss (low μ") materials but also with highly lossy materials (tan(δm)>>1). The second approach used to analyze MDWAs is through solving the Green function problem of the infinite magneto-dielectric cylinder fed by a current loop. This solution sheds light on the leaky and guided waves supported by the magneto-dielectric structure and leads to useful design rules connecting the permeability of the material to the cross sectional area of the antenna in relation to the desired frequency of operation. The Green function problem of the permeable prolate spheroidal antenna is also solved as a good approximation to a finite cylinder.
ContributorsSebastian, Tom (Author) / Diaz, Rodolfo E (Thesis advisor) / Pan, George (Committee member) / Aberle, James T., 1961- (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
A fully automated logic design methodology for radiation hardened by design (RHBD) high speed logic using fine grained triple modular redundancy (TMR) is presented. The hardening techniques used in the cell library are described and evaluated, with a focus on both layout techniques that mitigate total ionizing dose (TID) and latchup issues and flip-flop designs that mitigate single event transient (SET) and single event upset (SEU) issues. The base TMR self-correcting master-slave flip-flop is described and compared to more traditional hardening techniques. Additional refinements are presented, including testability features that disable the self-correction to allow detection of manufacturing defects. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. For synthesis and auto place and route, the methodology and circuits leverage commercial logic design automation tools. These tools are glued together with custom CAD tools designed to enable easy conversion of standard single redundant hardware description language (HDL) files into hardened TMR circuitry. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g. clock gating and supply voltage scaling.
ContributorsHindman, Nathan (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
Description
Analysing and measuring of biological or biochemical processes are of utmost importance for medical, biological and biotechnological applications. Point of care diagnostic system, composing of biosensors, have promising applications for providing cheap, accurate and portable diagnosis. Owing to these expanding medical applications and advances made by semiconductor industry biosensors have seen a tremendous growth in the past few decades. Also emergence of microfluidics and non-invasive biosensing applications are other marker propellers. Analyzing biological signals using transducers is difficult due to the challenges in interfacing an electronic system to the biological environment. Detection limit, detection time, dynamic range, specificity to the analyte, sensitivity and reliability of these devices are some of the challenges in developing and integrating these devices. Significant amount of research in the field of biosensors has been focused on improving the design, fabrication process and their integration with microfluidics to address these challenges. This work presents new techniques, design and systems to improve the interface between the electronic system and the biological environment. This dissertation uses CMOS circuit design to improve the reliability of these devices. Also this work addresses the challenges in designing the electronic system used for processing the output of the transducer, which converts biological signal into electronic signal.
ContributorsShah, Sahil S (Author) / Christen, Jennifer B (Thesis advisor) / Allee, David (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2014
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to 45nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22nm and 90nm nodes with less than a 5% error. Several other 90nm and 22nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H). Further capabilities of PANDA are demonstrated by the first full-chip silicon of PANDA which is implemented on 65nm process This system consists of a 24×25 cell array, reconfigurable interconnect and configuration memory. The voltage and current reference circuits, op amps and a VCO with a phase interpolation circuit are emulated by PANDA.
ContributorsSuh, Jounghyuk (Author) / Bakkaloglu, Bertan (Thesis advisor) / Cao, Yu (Committee member) / Ozev, Sule (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Due to diminishing availability of 3He, which is the critical component of neutron detecting proportional counters, large area flexible arrays are being considered as a potential replacement for neutron detection. A large area flexible array, utilizing semiconductors for both charged particle detection and pixel readout, ensures a large detection surface area in a light weight rugged form. Such a neutron detector could be suitable for deployment at ports of entry. The specific approach used in this research, uses a neutron converter layer which captures incident thermal neutrons, and then emits ionizing charged particles. These ionizing particles cause electron-hole pair generation within a single pixel's integrated sensing diode. The resulting charge is then amplified via a low-noise amplifier. This document begins by discussing the current state of the art in neutron detection and the associated challenges. Then, for the purpose of resolving some of these issues, recent design and modeling efforts towards developing an improved neutron detection system are described. Also presented is a low-noise active pixel sensor (APS) design capable of being implemented in low temperature indium gallium zinc oxide (InGaZnO) or amorphous silicon (a-Si:H) thin film transistor process compatible with plastic substrates. The low gain and limited scalability of this design are improved upon by implementing a new multi-stage self-resetting APS. For each APS design, successful radiation measurements are also presented using PiN diodes for charged particle detection. Next, detection array readout methodologies are modeled and analyzed, and use of a matched filter readout circuit is described as well. Finally, this document discusses detection diode integration with the designed TFT-based APSs.
ContributorsKunnen, George (Author) / Allee, David (Thesis advisor) / Garrity, Douglas (Committee member) / Gnade, Bruce (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2014
Description
There is an ever growing need for larger memories which are reliable and fast. New technologies to implement non-volatile memories which are large, fast, compact and cost-efficient are being studied extensively. One of the most promising technologies being developed is the resistive RAM (ReRAM). In ReRAM the resistance of the device varies with the voltage applied across it. Programmable metallization cells (PMC) is one of the devices belonging to this category of non-volatile memories.
In order to advance the development of these devices, there is a need to develop simulation models which replicate the behavior of these devices in circuits. In this thesis, a verilogA model for the PMC has been developed. The behavior of the model has been tested using DC and transient simulations. Experimental data obtained from testing PMC devices fabricated at Arizona State University have been compared to results obtained from simulation.
A basic memory cell known as the 1T 1R cell built using the PMC has also been simulated and verified. These memory cells have the potential to be building blocks of large scale memories. I believe that the verilogA model developed in this thesis will prove to be a powerful tool for researchers and circuit developers looking to develop non-volatile memories using alternative technologies.
In order to advance the development of these devices, there is a need to develop simulation models which replicate the behavior of these devices in circuits. In this thesis, a verilogA model for the PMC has been developed. The behavior of the model has been tested using DC and transient simulations. Experimental data obtained from testing PMC devices fabricated at Arizona State University have been compared to results obtained from simulation.
A basic memory cell known as the 1T 1R cell built using the PMC has also been simulated and verified. These memory cells have the potential to be building blocks of large scale memories. I believe that the verilogA model developed in this thesis will prove to be a powerful tool for researchers and circuit developers looking to develop non-volatile memories using alternative technologies.
ContributorsBharadwaj, Vineeth (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Mikkola, Esko (Committee member) / Arizona State University (Publisher)
Created2014
Description
Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while having maximal speed, capacity, retention time, and radiation hardness. A promising candidate for next-generation memory is ion-conducting bridging RAM which is referred to as programmable metallization cell (PMC), conductive bridge RAM (CBRAM), or electrochemical metallization memory (ECM), which is likely to surpass flash memory in all the ideal memory characteristics. A comprehensive physics-based model is needed to completely understand PMC operation and assist in design optimization.
To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities.
The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior.
The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.
To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities.
The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior.
The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.
ContributorsRajabi, Saba (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2014
Description
A new loop configuration capable of reducing power radiation magnitudes lower than conventional loops has been developed. This configuration is demonstrated for the case of two coaxial loops of 0.1 meter radius coupled via the magnetic reactive field. Utilizing electromagnetism theory, techniques from antenna design and a new near field design initiative, the ability to design a magnetic field has been investigated by using a full wave simulation tool. The method for realization is initiated from first order physics model, ADS and onto a full wave situation tool for the case of a non-radiating helical loop. The exploration into the design of a magnetic near field while mitigating radiation power is demonstrated using an real number of twists to form a helical wire loop while biasing the integer twisted loop in a non-conventional moebius termination. The helix loop setup as a moebius loop convention can also be expressed as a shorted antenna scheme. The 0.1 meter radius helix antenna is biased with a 1MHz frequency that categorized the antenna loop as electrically small. It is then demonstrated that helical configuration reduces the electric field and mitigates power radiation into the far field. In order to compare the radiated power reduction performance of the helical loop a shielded loop is used as a baseline for comparison. The shielded loop system of the same geometric size and frequency is shown to have power radiation expressed as -46.1 dBm. The power radiated mitigation method of the helix loop reduces the power radiated from the two loop system down to -98.72 dBm.
ContributorsMoreno, Fernando (Author) / Diaz, Rodolfo (Thesis advisor) / Aberle, James T., 1961- (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2015
Description
This work explores how flexible electronics and display technology can be applied to develop new biomedical devices for medical, biological, and life science applications. It demonstrates how new biomedical devices can be manufactured by only modifying or personalizing the upper layers of a conventional thin film transistor (TFT) display process. This personalization was applied first to develop and demonstrate the world's largest flexible digital x-ray detector for medical and industrial imaging, and the world's first flexible ISFET pH biosensor using TFT technology. These new, flexible, digital x-ray detectors are more durable than conventional glass substrate x-ray detectors, and also can conform to the surface of the object being imaged. The new flexible ISFET pH biosensors are >10X less expensive to manufacture than comparable CMOS-based ISFETs and provide a sensing area that is orders of magnitude larger than CMOS-based ISFETs. This allows for easier integration with area intensive chemical and biological recognition material as well as allow for a larger number of unique recognition sites for low cost multiple disease and pathogen detection.
The flexible x-ray detector technology was then extended to demonstrate the viability of a new technique to seamlessly combine multiple smaller flexible x-ray detectors into a single very large, ultimately human sized, composite x-ray detector for new medical imaging applications such as single-exposure, low-dose, full-body digital radiography. Also explored, is a new approach to increase the sensitivity of digital x-ray detectors by selectively disabling rows in the active matrix array that are not part of the imaged region. It was then shown how high-resolution, flexible, organic light-emitting diode display (OLED) technology can be used to selectively stimulate and/or silence small groups of neurons on the cortical surface or within the deep brain as a potential new tool to diagnose and treat, as well as understand, neurological diseases and conditions. This work also explored the viability of a new miniaturized high sensitivity fluorescence measurement-based lab-on-a-chip optical biosensor using OLED display and a-Si:H PiN photodiode active matrix array technology for point-of-care diagnosis of multiple disease or pathogen biomarkers in a low cost disposable configuration.
The flexible x-ray detector technology was then extended to demonstrate the viability of a new technique to seamlessly combine multiple smaller flexible x-ray detectors into a single very large, ultimately human sized, composite x-ray detector for new medical imaging applications such as single-exposure, low-dose, full-body digital radiography. Also explored, is a new approach to increase the sensitivity of digital x-ray detectors by selectively disabling rows in the active matrix array that are not part of the imaged region. It was then shown how high-resolution, flexible, organic light-emitting diode display (OLED) technology can be used to selectively stimulate and/or silence small groups of neurons on the cortical surface or within the deep brain as a potential new tool to diagnose and treat, as well as understand, neurological diseases and conditions. This work also explored the viability of a new miniaturized high sensitivity fluorescence measurement-based lab-on-a-chip optical biosensor using OLED display and a-Si:H PiN photodiode active matrix array technology for point-of-care diagnosis of multiple disease or pathogen biomarkers in a low cost disposable configuration.
ContributorsSmith, Joseph T. (Author) / Allee, David (Thesis advisor) / Goryll, Michael (Committee member) / Kozicki, Michael (Committee member) / Blain Christen, Jennifer (Committee member) / Couture, Aaron (Committee member) / Arizona State University (Publisher)
Created2014
Description
Several state of the art, monitoring and control systems, such as DC motor
controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
ContributorsThirunakkarasu, Shankar (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kozicki, Michael (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014