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- All Subjects: Electrical Engineering
- Creators: Ayyanar, Raja
- Creators: Chakrabarti, Chaitali
Description
With the increasing focus on developing environmentally benign electronic packages, lead-free solder alloys have received a great deal of attention. Mishandling of packages, during manufacture, assembly, or by the user may cause failure of solder joint. A fundamental understanding of the behavior of lead-free solders under mechanical shock conditions is lacking. Reliable experimental and numerical analysis of lead-free solder joints in the intermediate strain rate regime need to be investigated. This dissertation mainly focuses on exploring the mechanical shock behavior of lead-free tin-rich solder alloys via multiscale modeling and numerical simulations. First, the macroscopic stress/strain behaviors of three bulk lead-free tin-rich solders were tested over a range of strain rates from 0.001/s to 30/s. Finite element analysis was conducted to determine appropriate specimen geometry that could reach a homogeneous stress/strain field and a relatively high strain rate. A novel self-consistent true stress correction method is developed to compensate the inaccuracy caused by the triaxial stress state at the post-necking stage. Then the material property of micron-scale intermetallic was examined by micro-compression test. The accuracy of this measure is systematically validated by finite element analysis, and empirical adjustments are provided. Moreover, the interfacial property of the solder/intermetallic interface is investigated, and a continuum traction-separation law of this interface is developed from an atomistic-based cohesive element method. The macroscopic stress/strain relation and microstructural properties are combined together to form a multiscale material behavior via a stochastic approach for both solder and intermetallic. As a result, solder is modeled by porous plasticity with random voids, and intermetallic is characterized as brittle material with random vulnerable region. Thereafter, the porous plasticity fracture of the solders and the brittle fracture of the intermetallics are coupled together in one finite element model. Finally, this study yields a multiscale model to understand and predict the mechanical shock behavior of lead-free tin-rich solder joints. Different fracture patterns are observed for various strain rates and/or intermetallic thicknesses. The predictions have a good agreement with the theory and experiments.
ContributorsFei, Huiyang (Author) / Jiang, Hanqing (Thesis advisor) / Chawla, Nikhilesh (Thesis advisor) / Tasooji, Amaneh (Committee member) / Mobasher, Barzin (Committee member) / Rajan, Subramaniam D. (Committee member) / Arizona State University (Publisher)
Created2011
Description
Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming. This thesis proposes an analytical model to predict variability in CMOS circuits that is quick and accurate. There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ/μ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of Vth variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing Vth variation.
ContributorsGummalla, Samatha (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
The development of a Solid State Transformer (SST) that incorporates a DC-DC multiport converter to integrate both photovoltaic (PV) power generation and battery energy storage is presented in this dissertation. The DC-DC stage is based on a quad-active-bridge (QAB) converter which not only provides isolation for the load, but also for the PV and storage. The AC-DC stage is implemented with a pulse-width-modulated (PWM) single phase rectifier. A unified gyrator-based average model is developed for a general multi-active-bridge (MAB) converter controlled through phase-shift modulation (PSM). Expressions to determine the power rating of the MAB ports are also derived. The developed gyrator-based average model is applied to the QAB converter for faster simulations of the proposed SST during the control design process as well for deriving the state-space representation of the plant. Both linear quadratic regulator (LQR) and single-input-single-output (SISO) types of controllers are designed for the DC-DC stage. A novel technique that complements the SISO controller by taking into account the cross-coupling characteristics of the QAB converter is also presented herein. Cascaded SISO controllers are designed for the AC-DC stage. The QAB demanded power is calculated at the QAB controls and then fed into the rectifier controls in order to minimize the effect of the interaction between the two SST stages. The dynamic performance of the designed control loops based on the proposed control strategies are verified through extensive simulation of the SST average and switching models. The experimental results presented herein show that the transient responses for each control strategy match those from the simulations results thus validating them.
ContributorsFalcones, Sixifo Daniel (Author) / Ayyanar, Raja (Thesis advisor) / Karady, George G. (Committee member) / Tylavsky, Daniel (Committee member) / Tsakalis, Konstantinos (Committee member) / Arizona State University (Publisher)
Created2011
Description
Recent changes in the energy markets structure combined with the conti-nuous load growth have caused power systems to be operated under more stressed conditions. In addition, the nature of power systems has also grown more complex and dynamic because of the increasing use of long inter-area tie-lines and the high motor loads especially those comprised mainly of residential single phase A/C motors. Therefore, delayed voltage recovery, fast voltage collapse and short term voltage stability issues in general have obtained significant importance in relia-bility studies. Shunt VAr injection has been used as a countermeasure for voltage instability. However, the dynamic and fast nature of short term voltage instability requires fast and sufficient VAr injection, and therefore dynamic VAr devices such as Static VAr Compensators (SVCs) and STATic COMpensators (STAT-COMs) are used. The location and size of such devices are optimized in order to improve their efficiency and reduce initial costs. In this work time domain dy-namic analysis was used to evaluate trajectory voltage sensitivities for each time step. Linear programming was then performed to determine the optimal amount of required VAr injection at each bus, using voltage sensitivities as weighting factors. Optimal VAr injection values from different operating conditions were weighted and averaged in order to obtain a final setting of the VAr requirement. Some buses under consideration were either assigned very small VAr injection values, or not assigned any value at all. Therefore, the approach used in this work was found to be useful in not only determining the optimal size of SVCs, but also their location.
ContributorsSalloum, Ahmed (Author) / Vittal, Vijay (Thesis advisor) / Heydt, Gerald (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
Description
Redundant Binary (RBR) number representations have been extensively used in the past for high-throughput Digital Signal Processing (DSP) systems. Data-path components based on this number system have smaller critical path delay but larger area compared to conventional two's complement systems. This work explores the use of RBR number representation for implementing high-throughput DSP systems that are also energy-efficient. Data-path components such as adders and multipliers are evaluated with respect to critical path delay, energy and Energy-Delay Product (EDP). A new design for a RBR adder with very good EDP performance has been proposed. The corresponding RBR parallel adder has a much lower critical path delay and EDP compared to two's complement carry select and carry look-ahead adder implementations. Next, several RBR multiplier architectures are investigated and their performance compared to two's complement systems. These include two new multiplier architectures: a purely RBR multiplier where both the operands are in RBR form, and a hybrid multiplier where the multiplicand is in RBR form and the other operand is represented in conventional two's complement form. Both the RBR and hybrid designs are demonstrated to have better EDP performance compared to conventional two's complement multipliers. The hybrid multiplier is also shown to have a superior EDP performance compared to the RBR multiplier, with much lower implementation area. Analysis on the effect of bit-precision is also performed, and it is shown that the performance gain of RBR systems improves for higher bit precision. Next, in order to demonstrate the efficacy of the RBR representation at the system-level, the performance of RBR and hybrid implementations of some common DSP kernels such as Discrete Cosine Transform, edge detection using Sobel operator, complex multiplication, Lifting-based Discrete Wavelet Transform (9, 7) filter, and FIR filter, is compared with two's complement systems. It is shown that for relatively large computation modules, the RBR to two's complement conversion overhead gets amortized. In case of systems with high complexity, for iso-throughput, both the hybrid and RBR implementations are demonstrated to be superior with lower average energy consumption. For low complexity systems, the conversion overhead is significant, and overpowers the EDP performance gain obtained from the RBR computation operation.
ContributorsMahadevan, Rupa (Author) / Chakrabarti, Chaitali (Thesis advisor) / Kiaei, Sayfe (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
Description
This thesis investigated two different thermal flow sensors for intravascular shear stress analysis. They were based on heat transfer principle, which heat convection from the resistively heated element to the flowing fluid was measured as a function of the changes in voltage. For both sensors, the resistively heated elements were made of Ti/Pt strips with the thickness 0.12 µm and 0.02 µm. The resistance of the sensing element was measured at approximately 1.6-1.7 kohms;. A linear relation between the resistance and temperature was established over the temperature ranging from 22 degree Celsius to 80 degree Celsius and the temperature coefficient of resistance (TCR) was at approximately 0.12 %/degree Celsius. The first thermal flow sensor was one-dimensional (1-D) flexible shear stress sensor. The structure was sensing element sandwiched by a biocompatible polymer "poly-para-xylylene", also known as Parylene, which provided both insulation of electrodes and flexibility of the sensors. A constant-temperature (CT) circuit was designed as the read out circuit based on 0.6 µm CMOS (Complementary metal-oxide-semiconductor) process. The 1-D shear stress sensor suffered from a large measurement error. Because when the sensor was inserted into blood vessels, it was impossible to mount the sensor to the wall as calibrated in micro fluidic channels. According to the previous simulation work, the shear stress was varying and the sensor itself changed the shear stress distribution. We proposed a three-dimensional (3-D) thermal flow sensor, with three-axis of sensing elements integrated in one sensor. It was in the similar shape as a hexagonal prism with diagonal of 1000 µm. On the top of the sensor, there were five bond pads for external wires over 500 µm thick silicon substrate. In each nonadjacent side surface, there was a bended parylene branch with one sensing element. Based on the unique 3-D structure, the sensor was able to obtain data along three axes. With computational fluid dynamics (CFD) model, it is possible to locate the sensor in the blood vessels and give us a better understanding of shear stress distribution in the presence of time-varying component of blood flow and realize more accurate assessment of intravascular convective heat transfer.
ContributorsTang, Rui (Author) / Yu, Hongyu (Thesis advisor) / Jiang, Hanqing (Committee member) / Pan, George (Committee member) / Arizona State University (Publisher)
Created2011
Description
Due to restructuring and open access to the transmission system, modern electric power systems are being operated closer to their operational limits. Additionally, the secure operational limits of modern power systems have become increasingly difficult to evaluate as the scale of the network and the number of transactions between utilities increase. To account for these challenges associated with the rapid expansion of electric power systems, dynamic equivalents have been widely applied for the purpose of reducing the computational effort of simulation-based transient security assessment. Dynamic equivalents are commonly developed using a coherency-based approach in which a retained area and an external area are first demarcated. Then the coherent generators in the external area are aggregated and replaced by equivalenced models, followed by network reduction and load aggregation. In this process, an improperly defined retained area can result in detrimental impacts on the effectiveness of the equivalents in preserving the dynamic characteristics of the original unreduced system. In this dissertation, a comprehensive approach has been proposed to determine an appropriate retained area boundary by including the critical generators in the external area that are tightly coupled with the initial retained area. Further-more, a systematic approach has also been investigated to efficiently predict the variation in generator slow coherency behavior when the system operating condition is subject to change. Based on this determination, the critical generators in the external area that are tightly coherent with the generators in the initial retained area are retained, resulting in a new retained area boundary. Finally, a novel hybrid dynamic equivalent, consisting of both a coherency-based equivalent and an artificial neural network (ANN)-based equivalent, has been proposed and analyzed. The ANN-based equivalent complements the coherency-based equivalent at all the retained area boundary buses, and it is designed to compensate for the discrepancy between the full system and the conventional coherency-based equivalent. The approaches developed have been validated on a large portion of the Western Electricity Coordinating Council (WECC) system and on a test case including a significant portion of the eastern interconnection.
ContributorsMa, Feng (Author) / Vittal, Vijay (Thesis advisor) / Tylavsky, Daniel (Committee member) / Heydt, Gerald (Committee member) / Si, Jennie (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
Description
All-dielectric self-supporting (ADSS) fiber optic cables are used for data transfer by the utilities. They are installed along high voltage transmission lines. Dry band arcing, a phenomenon which is observed in outdoor insulators, is also observed in ADSS cables. The heat developed during dry band arcing damages the ADSS cables' outer sheath. A method is presented here to rate the cable sheath using the power developed during dry band arcing. Because of the small diameter of ADSS cables, mechanical vibration is induced in ADSS cable. In order to avoid damage, vibration dampers known as spiral vibration dampers (SVD) are used over these ADSS cables. These dampers are installed near the armor rods, where the presence of leakage current and dry band activity is more. The effect of dampers on dry band activity is investigated by conducting experiments on ADSS cable and dampers. Observations made from the experiments suggest that the hydrophobicity of the cable and damper play a key role in stabilizing dry band arcs. Hydrophobic-ity of the samples have been compared. The importance of hydrophobicity of the samples is further illustrated with the help of simulation results. The results indi-cate that the electric field increases at the edges of water strip. The dry band arc-ing phenomenon could thus be correlated to the hydrophobicity of the outer sur-face of cable and damper.
ContributorsPrabakar, Kumaraguru (Author) / Karady, George G. (Thesis advisor) / Vittal, Vijay (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
Description
The high penetration of photovoltaic (PV) both at the utility and at the distribu-tion levels, has raised concerns about the reliability of grid-tied inverters of PV power systems. Inverters are generally considered as the weak link in PV power systems. The lack of a dedicated qualification/reliability standard for PV inverters is a main barrier in realizing higher level of confidence in reliability. Development of a well-accepted design qualification standard specifically for PV inverters will help pave the way for significant improvement in reliability and performance of inverters across the entire industry. The existing standards for PV inverters such as UL 1741 and IEC 62109-1 primarily focus on safety. IEC 62093 discusses inverter qualification but it includes all the balance of sys-tem components and therefore not specific to PV inverters. There are other general stan-dards for distributed generators including the IEEE1547 series of standards which cover major concerns like utility integration but they are not dedicated to PV inverters and are not written from a design qualification point of view. In this thesis, some of the potential requirements for a design qualification standard for PV inverters are addressed. The IEC 62093 is considered as a guideline and the possible inclusions in the framework for a dedicated design qualification standard of PV inverter are discussed. The missing links in existing PV inverter related standards are identified by performing gap analysis. Dif-ferent requirements of small residential inverters compared to large utility-scale systems, and the emerging requirements on grid support features are also considered. Electric stress test is found to be the key missing link and one of the electric stress tests, the surge withstand test is studied in detail. The use of the existing standards for surge withstand test of residential scale PV inverters is investigated and a method to suitably adopt these standards is proposed. The proposed method is studied analytically and verified using simulation. A design criterion for choosing the switch ratings of the inverter that can per-form reliably under the surge environment is derived.
ContributorsAlampoondi Venkataramanan, Sai Balasubramanian (Author) / Ayyanar, Raja (Thesis advisor) / Vittal, Vijay (Committee member) / Heydt, Gerald (Committee member) / Arizona State University (Publisher)
Created2011
Description
High Voltage Direct Current (HVDC) technology is being considered for several long distance point-to-point overhead transmission lines, because of their lower losses and higher transmission capability, when compared to AC systems. Insulators are used to support and isolate the conductors mechanically and electrically. Composite insulators are gaining popularity for both AC and DC lines, for the reasons of light weight and good performance under contaminated conditions. This research illustrates the electric potential and field computation on HVDC composite insulators by using the charge simulation method. The electric field is calculated under both dry and wet conditions. Under dry conditions, the field distributions along the insulators whose voltage levels range from 500 kV to 1200 kV are calculated and compared. The results indicate that the HVDC insulator produces higher electric field, when compared to AC insulator. Under wet conditions, a 500 kV insulator is modeled with discrete water droplets on the surface. In this case, the field distribution is affected by surface resistivity and separations between droplets. The corona effects on insulators are analyzed for both dry and wet conditions. Corona discharge is created, when electric field strength exceeds the threshold value. Corona and grading rings are placed near the end-fittings of the insulators to reduce occurrence of corona. The dimensions of these rings, specifically their radius, tube thickness and projection from end fittings are optimized. This will help the utilities design proper corona and grading rings to reduce the corona phenomena.
ContributorsHe, Jiahong (Author) / Gorur, Ravi S (Committee member) / Ayyanar, Raja (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2013