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Description
As crystalline silicon solar cells continue to get thinner, the recombination of carriers at the surfaces of the cell plays an ever-important role in controlling the cell efficiency. One tool to minimize surface recombination is field effect passivation from the charges present in the thin films applied on the cell

As crystalline silicon solar cells continue to get thinner, the recombination of carriers at the surfaces of the cell plays an ever-important role in controlling the cell efficiency. One tool to minimize surface recombination is field effect passivation from the charges present in the thin films applied on the cell surfaces. The focus of this work is to understand the properties of charges present in the SiNx films and then to develop a mechanism to manipulate the polarity of charges to either negative or positive based on the end-application. Specific silicon-nitrogen dangling bonds (·Si-N), known as K center defects, are the primary charge trapping defects present in the SiNx films. A custom built corona charging tool was used to externally inject positive or negative charges in the SiNx film. Detailed Capacitance-Voltage (C-V) measurements taken on corona charged SiNx samples confirmed the presence of a net positive or negative charge density, as high as +/- 8 x 1012 cm-2, present in the SiNx film. High-energy (~ 4.9 eV) UV radiation was used to control and neutralize the charges in the SiNx films. Electron-Spin-Resonance (ESR) technique was used to detect and quantify the density of neutral K0 defects that are paramagnetically active. The density of the neutral K0 defects increased after UV treatment and decreased after high temperature annealing and charging treatments. Etch-back C-V measurements on SiNx films showed that the K centers are spread throughout the bulk of the SiNx film and not just near the SiNx-Si interface. It was also shown that the negative injected charges in the SiNx film were stable and present even after 1 year under indoor room-temperature conditions. Lastly, a stack of SiO2/SiNx dielectric layers applicable to standard commercial solar cells was developed using a low temperature (< 400 °C) PECVD process. Excellent surface passivation on FZ and CZ Si substrates for both n- and p-type samples was achieved by manipulating and controlling the charge in SiNx films.
ContributorsSharma, Vivek (Author) / Bowden, Stuart (Thesis advisor) / Schroder, Dieter (Committee member) / Honsberg, Christiana (Committee member) / Roedel, Ronald (Committee member) / Alford, Terry (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Increasing the conversion efficiencies of photovoltaic (PV) cells beyond the single junction theoretical limit is the driving force behind much of third generation solar cell research. Over the last half century, the experimental conversion efficiency of both single junction and tandem solar cells has plateaued as manufacturers and researchers have

Increasing the conversion efficiencies of photovoltaic (PV) cells beyond the single junction theoretical limit is the driving force behind much of third generation solar cell research. Over the last half century, the experimental conversion efficiency of both single junction and tandem solar cells has plateaued as manufacturers and researchers have optimized various materials and structures. While existing materials and technologies have remarkably good conversion efficiencies, they are approaching their own limits. For example, tandem solar cells are currently well developed commercially but further improvements through increasing the number of junctions struggle with various issues related to material interfacial defects. Thus, there is a need for novel theoretical and experimental approaches leading to new third generation cell structures. Multiple exciton generation (MEG) and intermediate band (IB) solar cells have been proposed as third generation alternatives and theoretical modeling suggests they can surpass the detailed balance efficiency limits of single junction and tandem solar cells. MEG or IB solar cell has a variety of advantages enabling the use of low bandgap materials. Integrating MEG and IB with other cell types to make novel solar cells (such as MEG with tandem, IB with tandem or MEG with IB) potentially offers improvements by employing multi-physics effects in one device. This hybrid solar cell should improve the properties of conventional solar cells with a reduced number of junction, increased light-generated current and extended material selections. These multi-physics effects in hybrid solar cells can be achieved through the use of nanostructures taking advantage of the carrier confinement while using existing solar cell materials with excellent characteristics. This reduces the additional cost to develop novel materials and structures. In this dissertation, the author develops thermodynamic models for several novel types of solar cells and uses these models to optimize and compare their properties to those of existing PV cells. The results demonstrate multiple advantages from combining MEG and IB technology with existing solar cell structures.
ContributorsLee, Jongwon (Author) / Honsberg, C. (Christiana B.) (Thesis advisor) / Bowden, Stuart (Committee member) / Roedel, Ronald (Committee member) / Goodnick, Stephen (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at

Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature. Therefore, the objective of this research was to characterize the electromigration lifetimes of passivated Au interconnects under precisely controlled stress conditions with statistically relevant quantities to obtain accurate model parameters essential for extrapolation to normal operational conditions. This research objective was accomplished through measurement of electromigration lifetimes of large quantities of passivated electroplated Au interconnects utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures. A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 ìm. All Au lifetime distributions followed log-normal distributions and Black's model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time.
ContributorsKilgore, Stephen (Author) / Adams, James (Thesis advisor) / Schroder, Dieter (Thesis advisor) / Krause, Stephen (Committee member) / Gaw, Craig (Committee member) / Arizona State University (Publisher)
Created2013
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Description
In the interest of expediting future pilot line start-ups for solar cell research, the development of Arizona State University's student-led pilot line at the Solar Power Laboratory is discussed extensively within this work. Several experiments and characterization techniques used to formulate and optimize a series of processes for fabricating diffused-junction,

In the interest of expediting future pilot line start-ups for solar cell research, the development of Arizona State University's student-led pilot line at the Solar Power Laboratory is discussed extensively within this work. Several experiments and characterization techniques used to formulate and optimize a series of processes for fabricating diffused-junction, screen-printed silicon solar cells are expounded upon. An experiment is conducted in which the thickness of a PECVD deposited anti-reflection coating (ARC) is varied across several samples and modeled as a function of deposition time. Using this statistical model in tandem with reflectance measurements for each sample, the ARC thickness is optimized to increase light trapping in the solar cells. A response surface model (RSM) experiment is conducted in which 3 process parameters are varied on the PECVD tool for the deposition of the ARCs on several samples. A contactless photoconductance decay (PCD) tool is used to measure the dark saturation currents of these samples. A statistical analysis is performed using JMP in which optimum deposition parameters are found. A separate experiment shows an increase in the passivation quality of the a-SiNx:H ARCs deposited on the solar cells made on the line using these optimum parameters. A RSM experiment is used to optimize the printing process for a particular silver paste in a similar fashion, the results of which are confirmed by analyzing the series resistance of subsequent cells fabricated on the line. An in-depth explanation of a more advanced analysis using JMP and PCD measurements on the passivation quality of 3 aluminum back-surface fields (BSF) is given. From this experiment, a comparison of the means is conducted in order to choose the most effective BSF paste for cells fabricated on the line. An experiment is conducted in parallel which confirms the results via Voc measurements. It is shown that in a period of 11 months, the pilot line went from producing a top cell efficiency of 11.5% to 17.6%. Many of these methods used for the development of this pilot line are equally applicable to other cell structures, and can easily be applied to other solar cell pilot lines.
ContributorsPickett, Guy (Author) / Bowden, Stuart (Thesis advisor) / Honsberg, Christiana (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Silicon (Si) solar cells are the dominant technology used in the Photovoltaics industry. Field-effect passivation by means of electrostatic charges stored in an overlying insulator on a silicon solar cell has been proven to be a significantly efficient way to reduce effective surface recombination velocity and increase minority carrier lifetime.

Silicon (Si) solar cells are the dominant technology used in the Photovoltaics industry. Field-effect passivation by means of electrostatic charges stored in an overlying insulator on a silicon solar cell has been proven to be a significantly efficient way to reduce effective surface recombination velocity and increase minority carrier lifetime. Silicon nitride (SiNx) films have been extensively used as passivation layers. The capability to store charges makes SiNx a promising material for excellent feild effect passivation. In this work, symmetrical Si/SiO2/SiNx stacks are developed to study the effect of charges in SiNx films. SiO2 films work as barrier layers. Corona charging technique showed the ability to inject charges into the SiNx films in a short time. Minority carrier lifetimes of the Czochralski (CZ) Si wafers increased significantly after either positive or negative charging. A fast and contactless method to characterize the charged overlying insulators on Si wafer through lifetime measurements is proposed and studied in this work, to overcome the drawbacks of capacitance-voltage (CV) measurements such as time consuming, induction of contanmination and hysteresis effect, etc. Analytical simulations showed behaviors of inverse lifetime (Auger corrected) vs. minority carrier density curves depend on insulator charge densities (Nf). From the curve behavior, the Si surface condition and region of Nf can be estimated. When the silicon surface is at high strong inversion or high accumulation, insulator charge density (Nf) or surface recombination velocity parameters (Sn0 and Sp0) can be determined from the slope of inverse lifetime curves, if the other variable is known. If Sn0 and Sp0 are unknown, Nf values of different samples can be compared as long as all have similar Sn0 and Sp0 values. Using the saturation current density (J0) and intercept fit extracted from the lifetime measurement, the bulk lifetime can be calculated. Therefore, this method is feasible and promising for charged insulator characterization.
ContributorsYang, Qun (Author) / Bowden, Stuart (Thesis advisor) / Honsberg, Christiana (Committee member) / Tracy, Clarence (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Crystalline silicon has a relatively low absorption coefficient, and therefore, in thin silicon solar cells surface texturization plays a vital role in enhancing light absorption. Texturization is needed to increase the path length of light through the active absorbing layer. The most popular choice for surface texturization of crystalline silicon

Crystalline silicon has a relatively low absorption coefficient, and therefore, in thin silicon solar cells surface texturization plays a vital role in enhancing light absorption. Texturization is needed to increase the path length of light through the active absorbing layer. The most popular choice for surface texturization of crystalline silicon is the anisotropic wet-etching that yields pyramid-like structures. These structures have shown to be both simple to fabricate and efficient in increasing the path length; they outperform most competing surface texture. Recent studies have also shown these pyramid-like structures are not truly square-based 54.7 degree pyramids but have variable base angles and shapes. In addition, their distribution is not regular -- as is often assumed in optical models -- but random. For accurate prediction of performance of silicon solar cells, it is important to investigate the true nature of the surface texture that is achieved using anisotropic wet-etching, and its impact on light trapping. We have used atomic force microscopy (AFM) to characterize the surface topology by obtaining actual height maps that serve as input to ray tracing software. The height map also yields the base angle distribution, which is compared to the base angle distribution obtained by analyzing the angular reflectance distribution measured by spectrophotometer to validate the shape of the structures. Further validation of the measured AFM maps is done by performing pyramid density comparison with SEM micrograph of the texture. Last method employed for validation is Focused Ion Beam (FIB) that is used to mill the long section of pyramids to reveal their profile and so from that the base angle distribution is measured. After that the measured map is modified and the maps are generated keeping the positional randomness (the positions of pyramids) and height of the pyramids the same, but changing their base angles. In the end a ray tracing software is used to compare the actual measured AFM map and also the modified maps using their reflectance, transmittance, angular scattering and most importantly path length enhancement, absorbance and short circuit current with lambertian scatterer.
ContributorsManzoor, Salman (Author) / Holman, Zachary (Thesis advisor) / Goodnick, Stephen (Committee member) / Bowden, Stuart (Committee member) / Arizona State University (Publisher)
Created2014
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Description
In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work,

In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work, the integration of random defects positioned across the channel at the Si:SiO2 interface from source end to the drain end in the presence of different random dopant distributions are used to conduct Ensemble Monte-Carlo ( EMC ) based numerical simulation of key device performance metrics for 45 nm gate length MOSFET device. The two main performance parameters that affect RTS based reliability measurements are percentage change in threshold voltage and percentage change in drain current fluctuation in the saturation region. It has been observed as a result of the simulation that changes in both and values moderately decrease as the defect position is gradually moved from source end to the drain end of the channel. Precise analytical device physics based model needs to be developed to explain and assess the EMC simulation based higher VT fluctuations as experienced for trap positions at the source side. A new analytical model has been developed that simultaneously takes account of dopant number variations in the channel and depletion region underneath and carrier mobility fluctuations resulting from fluctuations in surface potential barriers. Comparisons of this new analytical model along with existing analytical models are shown to correlate with 3D EMC simulation based model for assessment of VT fluctuations percentage induced by a single interface trap. With scaling of devices beyond 32 nm node, halo doping at the source and drain are routinely incorporated to combat the threshold voltage roll-off that takes place with effective channel length reduction. As a final study on this regard, 3D EMC simulation method based computations of threshold voltage fluctuations have been performed for varying source and drain halo pocket length to illustrate the threshold voltage fluctuations related reliability problems that have been aggravated by trap positions near the source at the interface compared to conventional 45 nm MOSFET.
ContributorsAshraf, Nabil Shovon (Author) / Vasileska, Dragica (Thesis advisor) / Schroder, Dieter (Committee member) / Goodnick, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
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Description
There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon

There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.
ContributorsSochacki, John (Author) / Thornton, Trevor J (Thesis advisor) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
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Description
The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated

The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.
ContributorsSanchez Esqueda, Ivan (Author) / Barnaby, Hugh J (Committee member) / Schroder, Dieter (Thesis advisor) / Schroder, Dieter K. (Committee member) / Holbert, Keith E. (Committee member) / Gildenblat, Gennady (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Programmable Metallization Cell (PMC) is a technology platform which utilizes mass transport in solid or liquid electrolyte coupled with electrochemical (redox) reactions to form or remove nanoscale metallic electrodeposits on or in the electrolyte. The ability to redistribute metal mass and form metallic nanostructure in or on a structure in

Programmable Metallization Cell (PMC) is a technology platform which utilizes mass transport in solid or liquid electrolyte coupled with electrochemical (redox) reactions to form or remove nanoscale metallic electrodeposits on or in the electrolyte. The ability to redistribute metal mass and form metallic nanostructure in or on a structure in situ, via the application of a bias on laterally placed electrodes, creates a large number of promising applications. A novel PMC-based lateral microwave switch was fabricated and characterized for use in microwave systems. It has demonstrated low insertion loss, high isolation, low voltage operation, low power and low energy consumption, and excellent linearity. Due to its non-volatile nature the switch operates with fewer biases and its simple planar geometry makes possible innovative device structures which can be potentially integrated into microwave power distribution circuits. PMC technology is also used to develop lateral dendritic metal electrodes. A lateral metallic dendritic network can be grown in a solid electrolyte (GeSe) or electrodeposited on SiO2 or Si using a water-mediated method. These dendritic electrodes grown in a solid electrolyte (GeSe) can be used to lower resistances for applications like self-healing interconnects despite its relatively low light transparency; while the dendritic electrodes grown using water-mediated method can be potentially integrated into solar cell applications, like replacing conventional Ag screen-printed top electrodes as they not only reduce resistances but also are highly transparent. This research effort also laid a solid foundation for developing dendritic plasmonic structures. A PMC-based lateral dendritic plasmonic structure is a device that has metallic dendritic networks grown electrochemically on SiO2 with a thin layer of surface metal nanoparticles in liquid electrolyte. These structures increase the distribution of particle sizes by connecting pre-deposited Ag nanoparticles into fractal structures and result in three significant effects, resonance red-shift, resonance broadening and resonance enhancement, on surface plasmon resonance for light trapping simultaneously, which can potentially enhance thin film solar cells' performance at longer wavelengths.
ContributorsRen, Minghan (Author) / Kozicki, Michael (Thesis advisor) / Schroder, Dieter (Committee member) / Roedel, Ronald (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2011