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This thesis work presents the design of the pixel readout circuit suitable for high speed and low light imaging application. The circuit is an improvement to the 6T pixel readout architecture. The designed readout circuit minimizes the leakage currents in the circuit and detects light producing a signal level of 350µV at the cathode of the photodiode. A novel layout technique is used for the pixel, which improves the fill factor of the pixel to 64.625%. The read out circuit designed is an integral part of high speed image sensor, which is fabricated using a 0.18 µm CMOS technology with the die size of 3.1mm x 3.4 mm, the pixel size of 20µm x 20 µm, number of pixel of 96 x 96 and four 10-bit pipelined ADC’s. The image sensor achieves a high frame rate of 10508 fps and readout speed of 96 M pixels / sec.
This thesis details the design process of a variable gain amplifier (VGA) based circuit which maintains a consistent output power over a wide range of input power signals. This effect is achieved by using power detection circuitry to adjust the gain of the VGA based on the current input power so that it is amplifier to a set power level. The paper details the theory behind this solutions as well as the design process which includes both simulations and physical testing of the actual circuit. It also analyses results of these tests and gives suggestions as to what could be done to further improve the design. The VGA based constant output power solution was designed as a section of a larger circuit which was developed as part of a senior capstone project, which is also briefly described in the paper.