Matching Items (102)
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- All Subjects: Electrical Engineering
- Creators: Holbert, Keith E.
- Creators: Karady, George G.
- Resource Type: Text
Description
A fully automated logic design methodology for radiation hardened by design (RHBD) high speed logic using fine grained triple modular redundancy (TMR) is presented. The hardening techniques used in the cell library are described and evaluated, with a focus on both layout techniques that mitigate total ionizing dose (TID) and latchup issues and flip-flop designs that mitigate single event transient (SET) and single event upset (SEU) issues. The base TMR self-correcting master-slave flip-flop is described and compared to more traditional hardening techniques. Additional refinements are presented, including testability features that disable the self-correction to allow detection of manufacturing defects. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. For synthesis and auto place and route, the methodology and circuits leverage commercial logic design automation tools. These tools are glued together with custom CAD tools designed to enable easy conversion of standard single redundant hardware description language (HDL) files into hardened TMR circuitry. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g. clock gating and supply voltage scaling.
ContributorsHindman, Nathan (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
Description
The dissolution of metal layers such as silver into chalcogenide glass layers such as germanium selenide changes the resistivity of the metal and chalcogenide films by a great extent. It is known that the incorporation of the metal can be achieved by ultra violet light exposure or thermal processes. In this work, the use of metal dissolution by exposure to gamma radiation has been explored for radiation sensor applications. Test structures were designed and a process flow was developed for prototype sensor fabrication. The test structures were designed such that sensitivity to radiation could be studied. The focus is on the effect of gamma rays as well as ultra violet light on silver dissolution in germanium selenide (Ge30Se70) chalcogenide glass. Ultra violet radiation testing was used prior to gamma exposure to assess the basic mechanism. The test structures were electrically characterized prior to and post irradiation to assess resistance change due to metal dissolution. A change in resistance was observed post irradiation and was found to be dependent on the radiation dose. The structures were also characterized using atomic force microscopy and roughness measurements were made prior to and post irradiation. A change in roughness of the silver films on Ge30Se70 was observed following exposure. This indicated the loss of continuity of the film which causes the increase in silver film resistance following irradiation. Recovery of initial resistance in the structures was also observed after the radiation stress was removed. This recovery was explained with photo-stimulated deposition of silver from the chalcogenide at room temperature confirmed with the re-appearance of silver dendrites on the chalcogenide surface. The results demonstrate that it is possible to use the metal dissolution effect in radiation sensing applications.
ContributorsChandran, Ankitha (Author) / Kozicki, Michael N (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
Microprocessors are the processing heart of any digital system and are central to all the technological advancements of the age including space exploration and monitoring. The demands of space exploration require a special class of microprocessors called radiation hardened microprocessors which are less susceptible to radiation present outside the earth's atmosphere, in other words their functioning is not disrupted even in presence of disruptive radiation. The presence of these particles forces the designers to come up with design techniques at circuit and chip levels to alleviate the errors which can be encountered in the functioning of microprocessors. Microprocessor evolution has been very rapid in terms of performance but the same cannot be said about its rad-hard counterpart. With the total data processing capability overall increasing rapidly, the clear lack of performance of the processors manifests as a bottleneck in any processing system. To design high performance rad-hard microprocessors designers have to overcome difficult design problems at various design stages i.e. Architecture, Synthesis, Floorplanning, Optimization, routing and analysis all the while maintaining circuit radiation hardness. The reference design `HERMES' is targeted at 90nm IBM G process and is expected to reach 500Mhz which is twice as fast any processor currently available. Chapter 1 talks about the mechanisms of radiation effects which cause upsets and degradation to the functioning of digital circuits. Chapter 2 gives a brief description of the components which are used in the design and are part of the consistent efforts at ASUVLSI lab culminating in this chip level implementation of the design. Chapter 3 explains the basic digital design ASIC flow and the changes made to it leading to a rad-hard specific ASIC flow used in implementing this chip. Chapter 4 talks about the triple mode redundant (TMR) specific flow which is used in the block implementation, delineating the challenges faced and the solutions proposed to make the flow work. Chapter 5 explains the challenges faced and solutions arrived at while using the top-level flow described in chapter 3. Chapter 6 puts together the results and analyzes the design in terms of basic integrated circuit design constraints.
ContributorsRamamurthy, Chandarasekaran (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh J (Committee member) / Mayhew, David (Committee member) / Arizona State University (Publisher)
Created2013
Description
Battery energy storage has shown a lot of potential in the recent past to be effective in various grid services due to its near instantaneous ramp rates and modularity. This thesis aims to determine the commercial viability of customer premises and substation sited battery energy storage systems. Five different types of services have been analyzed considering current market pricing of Lithium-ion batteries and power conditioning equipment. Energy Storage Valuation Tool 3.0 (Beta) has been used to exclusively determine the value of energy storage in the services analyzed. The results indicate that on the residential level, Lithium-ion battery energy storage may not be a cost beneficial option for retail tariff management or demand charge management as only 20-30% of the initial investment is recovered at the end of 15 year plant life. SRP's two retail Time-of-Use price plans E-21 and E-26 were analyzed in respect of their ability to increase returns from storage compared to those with flat pricing. It was observed that without a coupled PV component, E-21 was more suitable for customer premises energy storage, however, its revenue stream reduces with addition to PV. On the grid scale, however, with carefully chosen service hierarchy such as distribution investment deferral, spinning or balancing reserve support, the initial investment can be recovered to an extent of about 50-70%. The study done here is specific to Salt River Project inputs and data. Results for all the services analyzed are highly location specific and are only indicative of the overall viability and returns from them.
ContributorsNadkarni, Aditya (Author) / Karady, George G. (Thesis advisor) / Ayyanar, Raja (Committee member) / Hedman, Kory (Committee member) / Arizona State University (Publisher)
Created2013
Description
Voltage stability is always a major concern in power system operation. Recently Fault Induced Delayed Voltage Recovery (FIDVR) has gained increased attention. It is widely believed that the motor-driven loads of high efficiency, low inertia air conditioners are one of the main causes of FIDVR events. Simulation tools that assist power system operation and planning have been found insufficient to reproduce FIDVR events. This is because of their inaccurate load modeling of single-phase motor loads. Conventionally three-phase motor models have been used to represent the aggregation effect of single-phase motor load. However researchers have found that this modeling method is far from an accurate representation of single-phase induction motors. In this work a simulation method is proposed to study the precise influence of single-phase motor load in context of FIDVR. The load, as seen the transmission bus, is replaced with a detailed distribution system. Each single-phase motor in the distribution system is represented by an equipment-level model for best accuracy. This is to enable the simulation to capture stalling effects of air conditioner compressor motors as they are related to FIDVR events. The single phase motor models are compared against the traditional three phase aggregate approximation. Also different percentages of single-phase motor load are compared and analyzed. Simulation result shows that proposed method is able to reproduce FIDVR events. This method also provides a reasonable estimation of the power system voltage stability under the contingencies.
ContributorsMa, Yan (Author) / Karady, George G. (Thesis advisor) / Vittal, Vijay (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2012
Description
In the future electrical distribution system, it can be predicted that local power generators such as photovoltaic panels or wind turbines will play an important role in local distribution network. The local energy generation and local energy storage device can cause indeterminable power flow, and this could cause severe protection problems to existing simple overcurrent coordinated distribution protection system. An accurate, fast and reliable protection system based on pilot protection concept is proposed in this thesis. A comprehensive protection design specialized for the FREEDM system - the intelligent fault management (IFM) is presented in detail. In IFM, the pilot-differential protective method is employed as primary protection while the overcurrent protective method is employed as a backup protection. The IFM has been implemented by a real time monitoring program on LabVIEW. A complete sensitivity and selectivity analysis based on simulation is performed to evaluate the protection program performance under various system operating conditions. Followed by the sensitivity analysis, a case study of multiple-terminal model is presented with the possible challenges and potential limitation of the proposed protection system. Furthermore, a micro controller based on a protection system as hardware implementation is studied on a scaled physical test bed. The communication block and signal processing block are accomplished to establish cooperation between the micro-controller hardware and the IFM program. Various fault cases are tested. The result obtained shows that the proposed protection system successfully identifies faults on the test bed and the response time is approximately 1 cycle which is fast compared to the existing commercial protection systems and satisfies the FREEDM system requirement. In the end, an advanced system with faster, dedicated communication media is accomplished. By verifying with the virtual FREEDM system on RTDS, the correctness and the advantages of the proposed method are verified. An ultra fast protection system response time of 4ms is achieved, which is the fastest protection system for a distribution level electrical system.
ContributorsLiu, Xing (Author) / Karady, George G. (Thesis advisor) / Farmer, Richard (Committee member) / Ayyannar, Raja (Committee member) / Arizona State University (Publisher)
Created2012
Description
This thesis is focused on the study of wind energy integration and is divided into two segments. The first part of the thesis deals with developing a reliability evaluation technique for a wind integrated power system. A multiple-partial outage model is utilized to accurately calculate the wind generation availability. A methodology is presented to estimate the outage probability of wind generators while incorporating their reduced power output levels at low wind speeds. Subsequently, power system reliability is assessed by calculating the loss of load probability (LOLP) and the effect of wind integration on the overall system is analyzed. Actual generation and load data of the Texas power system in 2008 are used to construct a test case. To demonstrate the robustness of the method, relia-bility studies have been conducted for a fairly constant as well as for a largely varying wind generation profile. Further, the case of increased wind generation penetration level has been simulated and comments made about the usability of the proposed method to aid in power system planning in scenarios of future expansion of wind energy infrastructure. The second part of this thesis explains the development of a graphic user interface (GUI) to demonstrate the operation of a grid connected doubly fed induction generator (DFIG). The theory of DFIG and its back-to-back power converter is described. The GUI illustrates the power flow, behavior of the electrical circuit and the maximum power point tracking of the machine for a variable wind speed input provided by the user. The tool, although developed on MATLAB software platform, has been constructed to work as a standalone application on Windows operating system based computer and enables even the non-engineering students to access it. Results of both the segments of the thesis are discussed. Remarks are presented about the validity of the reliability technique and GUI interface for variable wind speed conditions. Improvements have been suggested to enable the use of the reliability technique for a more elaborate system. Recommendations have been made about expanding the features of the GUI tool and to use it to promote educational interest about renewable power engineering.
ContributorsSinha, Anubhav (Author) / Heydt, Gerald T (Thesis advisor) / Vittal, Vijay (Thesis advisor) / Ayyanar, Raja (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2012
Description
Polymeric materials containing nanometer (nm) size particles are being introduced to provide compact shapes for low and medium voltage insulation equipment. The nanocomposites may provide superior electrical performance when compared with those available currently, such as lower dielectric losses and increased dielectric strength, tracking and erosion resistance, and surface hydrophobicity. All of the above mentioned benefits can be achieved at a lower filler concentration (< 10%) than conventional microfillers (40-60%). Also, the uniform shapes of nanofillers provide a better electrical stress distribution as compared to irregular shaped microcomposites which can have high internal electric stress, which could be a problem for devices with active electrical parts. Improvement in electrical performance due to addition of nanofillers in an epoxy matrix has been evaluated in this work. Scanning Electron Microscopy (SEM) was done on the epoxy samples to confirm uniform dispersion of nano-sized fillers as good filler dispersion is essential to realize the above stated benefits. Dielectric spectroscopy experiments were conducted over a wide range of frequencies as a function of temperature to understand the role of space charge and interfaces in these materials. The experiment results demonstrate significant reduction in dielectric losses in samples containing nanofillers. High voltage experiments such as corona resistance tests were conducted over 500 hours to monitor degradation in the samples due to corona. These tests revealed improvements in partial discharge endurance of nanocomposite samples. These improvements could not be adequately explained using a macroscopic quantity such as thermal conductivity. Thermo gravimetric analysis (TGA) showed higher weight loss initiation temperatures for nanofilled samples which is in agreement with the corona resistance experimental results. Theoretical models have also been developed in this work to complement the results of the corona resistance experiment and the TGA analysis. Degradation model was developed to map the erosion path using Dijkstra's shortest path algorithm. A thermal model was developed to calculate the localized temperature distribution in the micro and nano-filled samples using the PDE toolbox in MATLAB. Both the models highlight the fact that improvement in nanocomposites is not limited to the filler concentrations that were tested experimentally.
ContributorsIyer, Ganpathy (Author) / Gorur, Ravi S (Thesis advisor) / Vittal, Vijay (Committee member) / Richert, Ranko (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2012
Description
This research presents potential and electric field calculations on medium voltage (MV) epoxy insulated outdoor current transformers (CTs) using a numeri-cal calculation approach. Two designs of MV dry-type epoxy insulated CTs were modeled using 3D field simulation software COULOMB® 9.0. Potential and elec-tric fields were calculated based on boundary element method. Different condi-tions such as dry exterior surface, wet exterior surface and internal voids were considered. The research demonstrates that the presence of internal conductors in CTs results in a less severe surface electric field distribution when compared to outdoor insulators of the same voltage range and type. The high electric field near the exited end triple-point of the CT reduces. This remained true even under wet conditions establishing better outdoor performance of CTs than outdoor insulators which have no internal conductors. The effect of internal conductors on voids within the insulation structure was also established. As a down side, internal voids in CTs experience higher electric field stress than in conductor-less insulators. The work recognizes that internal conducting parts in dry type CTs improves their outdoor performance when compared to electrical equipment without internal conductors.
ContributorsLakshmichand Jain, Sandeep Kumar (Author) / Gorur, Ravi (Thesis advisor) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2012
Description
The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design. Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.
ContributorsMaurya, Satendra Kumar (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Vrudhula, Sarma (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012