Matching Items (122)
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- All Subjects: Electrical Engineering
- Creators: Holbert, Keith E.
- Creators: Cao, Yu
- Resource Type: Text
Description
Renewable energy has been a very hot topic in recent years due to the traditional energy crisis. Incentives that encourage the renewables have been established all over the world. Ordinary homeowners are also seeking ways to exploit renewable energy. In this thesis, residential PV system, wind turbine system and a hybrid wind/solar system are all investigated. The solar energy received by the PV panels varies with many factors. The most essential one is the irradiance. As the PV panel been installed towards different orientations, the incident insolation received by the panel also will be different. The differing insolation corresponds to the different angles between the irradiance and the panel throughout the day. The result shows that for PV panels in the northern hemisphere, the ones facing south obtain the highest level insolation and thus generate the most electricity. However, with the two different electricity rate plans, flat rate plan and TOU (time of use) plan, the value of electricity that PV generates is different. For wind energy, the wind speed is the most significant variable to determine the generation of a wind turbine. Unlike solar energy, wind energy is much more regionally dependent. Wind resources vary between very close locations. As expected, the result shows that, larger wind speed leads to more electricity generation and thus shorter payback period. For the PV/wind hybrid system, two real cases are analyzed for Altamont and Midhill, CA. In this part, the impact of incentives, system cost and system size are considered. With a hybrid system, homeowners may choose different size combinations between PV and wind turbines. It turns out that for these two locations, the system with larger PV output always achieve a shorter payback period due to the lower cost. Even though, for a longer term, the system with a larger wind turbine in locations with excellent wind resources may lead to higher return on investment. Meanwhile, impacts of both wind and solar incentives (mainly utility rebates) are analyzed. At last, effects of the cost of both renewables are performed.
ContributorsAn, Wen (Author) / Holbert, Keith E. (Thesis advisor) / Karady, George G. (Committee member) / Tylavsky, Daniel (Committee member) / Arizona State University (Publisher)
Created2012
Description
In this thesis, an issue is post at the beginning, that there is limited experience in connecting a battery analytical model with a battery circuit model. Then it describes the process of creating a new battery circuit model which is referred to as the kinetic battery model. During this process, a new general equation is derived. The original equation in the kinetic battery model is only valid at a constant current rate, while the new equation can be used for not only constant current but also linear or nonlinear current. Following the new equation, a circuit representation is built based on the kinetic battery model. Then, by matching the two sets of differential equations of the two models together, the ability to connect the analytical model with the battery circuit model is found. To verify the new battery circuit model is built correctly, the new circuit model is implemented into PSpice simulation software to test the charging performance with constant current, and Matlab/Simulink is also employed to simulate a realistic battery charging process with two-stage charging method. The results have shown the new circuit model is available to be used in realistic scenarios. And because the kinetic battery model can describe different types of rechargeable batteries, the new circuit model is also capable to be used for various battery types.
ContributorsKong, Dexinghui (Author) / Holbert, Keith E. (Thesis advisor) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2012
Description
Power generation in remote isolated places is a tough problem. Presently, a common source for remote generation is diesel. However, diesel generation is costly and environmental unfriendly. It is promising to replace the diesel generation with some clean and economical generation sources. The concept of renewable generation offers a solution to remote generation. This thesis focuses on evaluation of renewable generation penetration in the remote isolated grid. A small town named Coober Pedy in South Australia is set as an example. The first task is to build the stochastic models of solar irradiation and wind speed based on the local historical data. With the stochastic models, generation fluctuations and generation planning are further discussed. Fluctuation analysis gives an evaluation of storage unit size and costs. Generation planning aims at finding the relationships between penetration level and costs under constraint of energy sufficiency. The results of this study provide the best penetration level that makes the minimum energy costs. In the case of Coober Pedy, cases of wind and photovoltaic penetrations are studied. The additional renewable sources and suspended diesel generation change the electricity costs. Results show that in remote isolated grid, compared to diesel generation, renewable generation can lower the energy costs.
ContributorsZhu, Yujia (Author) / Holbert, Keith E. (Thesis advisor) / Karady, George G. (Committee member) / Tylavsky, Daniel J (Committee member) / Arizona State University (Publisher)
Created2012
Description
In this thesis two methodologies have been proposed for evaluating the fault response of analog/RF circuits. These proposed approaches are used to evaluate the response of the faulty circuit in terms of specifications/measurements. Faulty response can be used to evaluate important test metrics like fail probability, fault coverage and yield coverage of given measurements under process variations. Once the models for faulty and fault free circuit are generated, one needs to perform Monte Carlo sampling (as opposed to Monte Carlo simulations) to compute these statistical parameters with high accuracy. The first method is based on adaptively determining the order of the model based on the error budget in terms of computing the statistical metrics and position of the threshold(s) to decide how precisely necessary models need to be extracted. In the second method, using hierarchy in process variations a hybrid of heuristics and localized linear models have been proposed. Experiments on LNA and Mixer using the adaptive model order selection procedure can reduce the number of necessary simulations by 7.54x and 7.03x respectively in the computation of fail probability for an error budget of 2%. Experiments on LNA using the hybrid approach can reduce the number of necessary simulations by 21.9x and 17x for four and six output parameters cases for improved accuracy in test statistics estimation.
ContributorsSubrahmaniyan Radhakrishnan, Gurusubrahmaniyan (Author) / Ozev, Sule (Thesis advisor) / Blain Christen, Jennifer (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2010
Description
To extend the lifetime of complementary metal-oxide-semiconductors (CMOS), emerging process techniques are being proposed to conquer the manufacturing difficulties. New structures and materials are proposed with superior electrical properties to traditional CMOS, such as strain technology and feedback field-effect transistor (FB-FET). To continue the design success and make an impact on leading products, advanced circuit design exploration must begin concurrently with early silicon development. Therefore, an accurate and scalable model is desired to correctly capture those effects and flexible to extend to alternative process choices. For example, strain technology has been successfully integrated into CMOS fabrication to improve transistor performance but the stress is non-uniformly distributed in the channel, leading to systematic performance variations. In this dissertation, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. On the other hand, semiconductor devices with self-feedback mechanisms are emerging as promising alternatives to CMOS. Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure. Under particular circumstances, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. A new threshold voltage model for Fe-FET is developed, and is further revealed that the impact of random dopant fluctuation (RDF) can be suppressed. Furthermore, through silicon via (TSV), a key technology that enables the 3D integration of chips, is studied. TSV structure is usually a cylindrical metal-oxide-semiconductors (MOS) capacitor. A piecewise capacitance model is proposed for 3D interconnect simulation. Due to the mismatch in coefficients of thermal expansion (CTE) among materials, thermal stress is observed in TSV process and impacts neighboring devices. The stress impact is investigated to support the interaction between silicon process and IC design at the early stage.
ContributorsWang, Chi-Chao (Author) / Cao, Yu (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Clark, Lawrence (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2011
Description
Optical Instrument Transformers (OIT) have been developed as an alternative to traditional instrument transformers (IT). The question "Can optical instrument transformers substitute for the traditional transformers?" is the main motivation of this study. Finding the answer for this question and developing complete models are the contributions of this work. Dedicated test facilities are developed so that the steady state and transient performances of analog outputs of a magnetic current transformer (CT) and a magnetic voltage transformer (VT) are compared with that of an optical current transformer (OCT) and an optical voltage transformer (OVT) respectively. Frequency response characteristics of OIT outputs are obtained. Comparison results show that OITs have a specified accuracy of 0.3% in all cases. They are linear, and DC offset does not saturate the systems. The OIT output signal has a 40~60 μs time delay, but this is typically less than the equivalent phase difference permitted by the IEEE and IEC standards for protection applications. Analog outputs have significantly higher bandwidths (adjustable to 20 to 40 kHz) than the IT. The digital output signal bandwidth (2.4 kHz) of an OCT is significantly lower than the analog signal bandwidth (20 kHz) due to the sampling rates involved. The OIT analog outputs may have significant white noise of 6%, but the white noise does not affect accuracy or protection performance. Temperatures up to 50oC do not adversely affect the performance of the OITs. Three types of models are developed for analog outputs: analog, digital, and complete models. Well-known mathematical methods, such as network synthesis and Jones calculus methods are applied. The developed models are compared with experiment results and are verified with simulation programs. Results show less than 1.5% for OCT and 2% for OVT difference and that the developed models can be used for power system simulations and the method used for the development can be used to develop models for all other brands of optical systems. The communication and data transfer between the all-digital protection systems is investigated by developing a test facility for all digital protection systems. Test results show that different manufacturers' relays and transformers based on the IEC standard can serve the power system successfully.
ContributorsKucuksari, Sadik (Author) / Karady, George G. (Thesis advisor) / Heydt, Gerald T (Committee member) / Holbert, Keith E. (Committee member) / Ayyanar, Raja (Committee member) / Farmer, Richard (Committee member) / Arizona State University (Publisher)
Created2010
Description
The RADiation sensitive Field Effect Transistor (RADFET) has been conventionally used to measure radiation dose levels. These dose sensors are calibrated in such a way that a shift in threshold voltage, due to a build-up of oxide-trapped charge, can be used to estimate the radiation dose. In order to estimate the radiation dose level using RADFET, a wired readout circuit is necessary. Using the same principle of oxide-trapped charge build-up, but by monitoring the change in capacitance instead of threshold voltage, a wireless dose sensor can be developed. This RADiation sensitive CAPacitor (RADCAP) mounted on a resonant patch antenna can then become a wireless dose sensor. From the resonant frequency, the capacitance can be extracted which can be mapped back to estimate the radiation dose level. The capacitor acts as both radiation dose sensor and resonator element in the passive antenna loop. Since the MOS capacitor is used in passive state, characterizing various parameters that affect the radiation sensitivity is essential. Oxide processing technique, choice of insulator material, and thickness of the insulator, critically affect the dose response of the sensor. A thicker oxide improves the radiation sensitivity but reduces the dynamic range of dose levels for which the sensor can be used. The oxide processing scheme primarily determines the interface trap charge and oxide-trapped charge development; controlling this parameter is critical to building a better dose sensor.
ContributorsSrinivasan Gopalan, Madusudanan (Author) / Barnaby, Hugh (Thesis advisor) / Holbert, Keith E. (Committee member) / Yu, Hongyu (Committee member) / Arizona State University (Publisher)
Created2010
Description
The diagnosis for an attention deficit/hyperactivity disorder (ADHD) in children is heavily based on teacher or parent opinion, and not on scientific evidence. This causes children to be wrongly diagnosed with a disorder and be prescribed medicine that they do not need to be taking. This paper discusses a project that was completed for the Child Study Lab (CSL) preschool at Arizona State University (ASU), in which children’s activity within a classroom was automatically recorded using ultra-wideband technology. This project’s goal was to gather location data on the children in the CSL and analyze and assess the collected data for any patterns of behavior. The hope was that if a child’s data displayed a pattern that strayed from the norm, that this analysis could pose as a more objective way to indicate that a child may have an attention deficit problem. Fractal Dimensions and Levy Flights were researched and applied to the data analysis portion of this project.
ContributorsKjerstad, Kamryn R (Author) / Kozicki, Michael (Thesis director) / Kupfer, Anne (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2020-05
Description
Convolutional neural networks(CNNs) achieve high accuracy on large datasets but requires significant computation and storage requirement for training/testing. While many applications demand low latency and energy-efficient processing of the images, deploying these complex algorithms on the hardware is a challenging task. This dissertation first presents a compiler-based CNN training accelerator using DDR3 and HBM2 memory. An optimized RTL library is implemented to perform training-specific tasks and an RTL compiler is developed to generate FPGA-synthesizable RTL based on user-defined constraints. High Bandwidth Memory(HBM) provides efficient off-chip communication and improves the training performance. The impact of HBM2 on CNN training workloads is analyzed and compressively compared with DDR3. For training ResNet-20/VGG-like CNNs for the CIFAR-10 dataset, the proposed CNN training accelerator on Stratix-10 GX FPGA(DDR3) demonstrates 479 GOPS performance, and on Stratix-10 MX FPGA(HBM) shows 4.5/9.7 X energy-efficiency improvement compared to Tesla V100 GPU. Next, the FPGA online learning accelerator is presented. Adopting model segmentation techniques from Progressive Segmented Training(PST), the online learning accelerator achieved a 4.2X reduction in training latency. Furthermore, this dissertation presents an 8-bit floating-point (FP8) training processor which implements (1) Highly parallel tensor cores that maintain high PE utilization, (2) Hardware-efficient channel gating for dynamic output activation sparsity (3) Dynamic weight sparsity based on group Lasso (4) Gradient skipping based on FP prediction error. The 28nm prototype chip demonstrates significant improvements in FLOPs reduction (7.3×), energy efficiency (16.4 TFLOPS/W), and overall training latency speedup (4.7×) for both supervised training and self-supervised training tasks. In addition to the training accelerators, this dissertation also presents a CNN inference accelerator on ASIC(FixyNN) and FPGA(FixyFPGA). FixyNN consists of a fixed-weight feature extractor that generates ubiquitous CNN features and a conventional programmable CNN accelerator. In the fixed-weight feature extractor, the network weights are hard-coded into hardware and used as a fixed operand for the multiplication. Experimental results demonstrate FixyNN can achieve very high energy efficiencies up to 26.6 TOPS/W, and FixyFPGA achieves $2.34\times$ higher GOPS on ImageNet classification. In summary, this dissertation comprehensively discusses novel architectures of high-performance and energy-efficient ASIC/FPGA CNN inference/training accelerators.
ContributorsKolala Venkataramaniah, Shreyas (Author) / Seo, Jae-Sun (Thesis advisor) / Cao, Yu (Committee member) / Chakrabarti, Chaitali (Committee member) / Fan, Deliang (Committee member) / Arizona State University (Publisher)
Created2022
Description
Artificial Intelligence (AI) and Machine Learning (ML) techniques have come a long way since their inception and have been used to build intelligent systems for a wide range of applications in everyday life. However they are very computationintensive and require transfer of large volume of data from memory to the computation units. This memory access time constitute significant part of the computational latency and a performance bottleneck. To address this limitation and the ever-growing demand for implementation in hand-held and edge-devices, In-memory computing (IMC) based AI/ML hardware accelerators have emerged. First, the dissertation presents an IMC static random access memory (SRAM) based hardware modeling and optimization framework. A unified systematic study closely models the IMC hardware, and investigates how a number of design variables and non-idealities (e.g. device mismatch and ADC quantization) affect the Deep Neural Network (DNN) accuracy of the IMC design. The framework allows co-optimized selection of different design variables accounting for sources of noise in IMC hardware and robust implementation of a high accuracy DNN. Next, it presents a kNN hardware accelerator in 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The accelerator combines an IMC SRAM that is developed for binarized deep neural networks and other digital hardware that performs top-k sorting. The simulated k Nearest Neighbor accelerator design processes up to 17.9 million query vectors per second while consuming 11.8 mW, demonstrating >4.8× energy-efficiency improvement over prior works. This dissertation also presents a novel floating-point precision IMC (FP-IMC) macro with a hybrid architecture that configurably supports two Floating Point (FP) precisions. Implementing FP precision MAC has been a challenge owing to its complexity. The design is implemented on 28nm CMOS, and taped-out on chip demonstrating 12.1 TFLOPS/W and 66.1 TFLOPS/W for 8-bit Floating Point (FP8) and Block Floating point (BF8) respectively. Finally, another iteration of the FP design is presented that is modeled to support multiple precision modes from FP8 up to FP32. Two approaches to the architectural design were compared illustrating the throughput-area overhead trade-off. The simulated design shows a 2.1 × normalized energy-efficiency compared to the on-chip implementation of the FP-IMC.
ContributorsSaikia, Jyotishman (Author) / Seo, Jae-Sun (Thesis advisor) / Chakrabarti, Chaitali (Thesis advisor) / Fan, Deliang (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2023