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Description
Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for example at room temperature, InAs field effect transistor (FET) has electron mobility of 40,000 cm2/Vs more than 10 times of Si FET. This makes such materials promising for high speed nanowire FETs. With small bandgap, such as 0.354 eV for InAs and 1.52 eV for GaAs, it does not need high voltage to turn on such devices which leads to low power consumption devices. Another feature of direct bandgap allows their applications of optoelectronic devices such as avalanche photodiodes. However, there are challenges to face up. Due to their large surface to volume ratio, nanowire devices typically are strongly affected by the surface states. Although nanowires can be grown into single crystal structure, people observe crystal defects along the wires which can significantly affect the performance of devices. In this work, FETs made of two types of III-V nanowire, GaAs and InAs, are demonstrated. These nanowires are grown by catalyst-free MOCVD growth method. Vertically nanowires are transferred onto patterned substrates for coordinate calibration. Then electrodes are defined by e-beam lithography followed by deposition of contact metals. Prior to metal deposition, however, the substrates are dipped in ammonium hydroxide solution to remove native oxide layer formed on nanowire surface. Current vs. source-drain voltage with different gate bias are measured at room temperature. GaAs nanowire FETs show photo response while InAs nanowire FETs do not show that. Surface passivation is performed on GaAs FETs by using ammonium surfide solution. The best results on current increase is observed with around 20-30 minutes chemical treatment time. Gate response measurements are performed at room temperature, from which field effect mobility as high as 1490 cm2/Vs is extracted for InAs FETs. One major contributor for this is stacking faults defect existing along nanowires. For InAs FETs, thermal excitations observed from temperature dependent results which leads us to investigate potential barriers.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Ferry, David (Committee member) / Tracy, Clarence (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT An Ensemble Monte Carlo (EMC) computer code has been developed to simulate, semi-classically, spin-dependent electron transport in quasi two-dimensional (2D) III-V semiconductors. The code accounts for both three-dimensional (3D) and quasi-2D transport, utilizing either 3D or 2D scattering mechanisms, as appropriate. Phonon, alloy, interface roughness, and impurity scattering mechanisms are included, accounting for the Pauli Exclusion Principle via a rejection algorithm. The 2D carrier states are calculated via a self-consistent 1D Schrödinger-3D-Poisson solution in which the charge distribution of the 2D carriers in the quantization direction is taken as the spatial distribution of the squared envelope functions within the Hartree approximation. The wavefunctions, subband energies, and 2D scattering rates are updated periodically by solving a series of 1D Schrödinger wave equations (SWE) over the real-space domain of the device at fixed time intervals. The electrostatic potential is updated by periodically solving the 3D Poisson equation. Spin-polarized transport is modeled via a spin density-matrix formalism that accounts for D'yakanov-Perel (DP) scattering. Also, the code allows for the easy inclusion of additional scattering mechanisms and structural modifications to devices. As an application of the simulator, the current voltage characteristics of an InGaAs/InAlAs HEMT are simulated, corresponding to nanoscale III-V HEMTs currently being fabricated by Intel Corporation. The comparative effects of various scattering parameters, material properties and structural attributes are investigated and compared with experiments where reasonable agreement is obtained. The spatial evolution of spin-polarized carriers in prototypical Spin Field Effect Transistor (SpinFET) devices is then simulated. Studies of the spin coherence times in quasi-2D structures is first investigated and compared to experimental results. It is found that the simulated spin coherence times for GaAs structures are in reasonable agreement with experiment. The SpinFET structure studied is a scaled-down version of the InGaAs/InAlAs HEMT discussed in this work, in which spin-polarized carriers are injected at the source, and the coherence length is studied as a function of gate voltage via the Rashba effect.
ContributorsTierney, Brian David (Author) / Goodnick, Stephen (Thesis advisor) / Ferry, David (Committee member) / Akis, Richard (Committee member) / Saraniti, Marco (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
Description
A novel strain sensing procedure using an optical scanning methodology and diffraction grating is explored. The motivation behind this study is due to uneven thermal strain distribution across semiconductor chips that are composed of varying materials. Due to the unique properties of the materials and the different coefficients of thermal expansion (CTE), one can expect the material that experiences the highest strain to be the most likely failure point of the chip. As such, there is a need for a strain sensing technique that offers a very high strain sensitivity, a high spatial resolution while simultaneously achieving a large field of view. This study goes through the optical setup as well as the evolution of the optical grating in an effort to improve the strain sensitivity of this setup.
ContributorsChen, George (Co-author) / Ma, Teng (Co-author) / Liang, Hanshuang (Co-author) / Song, Zeming (Co-author) / Nguyen, Hoa (Co-author) / Yu, Hongbin (Thesis director) / Jiang, Hanqing (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2014-05
Description
Graphene, a one atomic thick planar sheet of carbon atoms, has a zero gap band structure with a linear dispersion relation. This unique property makes graphene a favorite for physicists and engineers, who are trying to understand the mechanism of charge transport in graphene and using it as channel material for field effect transistor (FET) beyond silicon. Therefore, an in-depth exploring of these electrical properties of graphene is urgent, which is the purpose of this dissertation. In this dissertation, the charge transport and quantum capacitance of graphene were studied. Firstly, the transport properties of back-gated graphene transistor covering by high dielectric medium were systematically studied. The gate efficiency increased by up to two orders of magnitude in the presence of a high top dielectric medium, but the mobility did not change significantly. The results strongly suggested that the previously reported top dielectric medium-induced charge transport properties of graphene FETs were possibly due to the increase of gate capacitance, rather than enhancement of carrier mobility. Secondly, a direct measurement of quantum capacitance of graphene was performed. The quantum capacitance displayed a non-zero minimum at the Dirac point and a linear increase on both sides of the minimum with relatively small slopes. The findings - which were not predicted by theory for ideal graphene - suggested that scattering from charged impurities also influences the quantum capacitance. The capacitances in aqueous solutions at different ionic concentrations were also measured, which strongly suggested that the longstanding puzzle about the interfacial capacitance in carbon-based electrodes had a quantum origin. Finally, the transport and quantum capacitance of epitaxial graphene were studied simultaneously, the quantum capacitance of epitaxial graphene was extracted, which was similar to that of exfoliated graphene near the Dirac Point, but exhibited a large sub-linear behavior at high carrier density. The self-consistent theory was found to provide a reasonable description of the transport data of the epitaxial graphene device, but a more complete theory was needed to explain both the transport and quantum capacitance data.
ContributorsXia, Jilin (Author) / Tao, N.J. (Thesis advisor) / Ferry, David (Committee member) / Thornton, Trevor (Committee member) / Tsui, Raymond (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2010
Description
Moore's law has been the most important driving force for the tremendous progress of semiconductor industry. With time the transistors which form the fundamental building block of any integrated circuit have been shrinking in size leading to smaller and faster electronic devices.As the devices scale down thermal effects and the short channel effects become the important deciding factors in determining transistor architecture.SOI (Silicon on Insulator) devices have been excellent alternative to planar MOSFET for ultimate CMOS scaling since they mitigate short channel effects. Hence as a part of thesis we tried to study the benefits of the SOI technology especially for lower technology nodes when the channel thickness reduces down to sub 10nm regime. This work tries to explore the effects of structural confinement due to reduced channel thickness on the electrostatic behavior of DG SOI MOSFET. DG SOI MOSFET form the Qfinfet which is an alternative to existing Finfet structure. Qfinfet was proposed and patented by the Finscale Inc for sub 10nm technology nodes.
As part of MS Thesis we developed electrostatic simulator for DG SOI devices by implementing the self consistent full band Schrodinger Poisson solver. We used the Empirical Pseudopotential method in conjunction with supercell approach to solve the Schrodinger Equation. EPM was chosen because it has few empirical parameters which give us good accuracy for experimental results. Also EPM is computationally less expensive as compared to the atomistic methods like DFT(Density functional theory) and NEGF (Non-equilibrium Green's function). In our workwe considered two crystallographic orientations of Si,namely [100] and [110].
As part of MS Thesis we developed electrostatic simulator for DG SOI devices by implementing the self consistent full band Schrodinger Poisson solver. We used the Empirical Pseudopotential method in conjunction with supercell approach to solve the Schrodinger Equation. EPM was chosen because it has few empirical parameters which give us good accuracy for experimental results. Also EPM is computationally less expensive as compared to the atomistic methods like DFT(Density functional theory) and NEGF (Non-equilibrium Green's function). In our workwe considered two crystallographic orientations of Si,namely [100] and [110].
ContributorsLaturia, Akash (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2016
Description
Thermal effects in nano-scaled devices were reviewed and modeling methodologies to deal with this issue were discussed. The phonon energy balance equations model, being one of the important previous works regarding the modeling of heating effects in nano-scale devices, was derived. Then, detailed description was given on the Monte Carlo (MC) solution of the phonon Boltzmann Transport Equation. The phonon MC solver was developed next as part of this thesis. Simulation results of the thermal conductivity in bulk Si show good agreement with theoretical/experimental values from literature.
ContributorsYoo, Seung Kyung (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2015
Description
In this work, a highly sensitive strain sensing technique is developed to realize in-plane strain mapping for microelectronic packages or emerging flexible or foldable devices, where mechanical or thermal strain is a major concern that could affect the performance of the working devices or even lead to the failure of the devices. Therefore strain sensing techniques to create a contour of the strain distribution is desired.
The developed highly sensitive micro-strain sensing technique differs from the existing strain mapping techniques, such as digital image correlation (DIC)/micro-Moiré techniques, in terms of working mechanism, by filling a technology gap that requires high spatial resolution while simultaneously maintaining a large field-of-view. The strain sensing mechanism relies on the scanning of a tightly focused laser beam onto the grating that is on the sample surface to detect the change in the diffracted beam angle as a result of the strain. Gratings are fabricated on the target substrates to serve as strain sensors, which carries the strain information in the form of variations in the grating period. The geometric structure of the optical system inherently ensures the high sensitivity for the strain sensing, where the nanoscale change of the grating period is amplified by almost six orders into a diffraction peak shift on the order of several hundred micrometers. It significantly amplifies the small signal measurements so that the desired sensitivity and accuracy can be achieved.
The important features, such as strain sensitivity and spatial resolution, for the strain sensing technique are investigated to evaluate the technique. The strain sensitivity has been validated by measurements on homogenous materials with well known reference values of CTE (coefficient of thermal expansion). 10 micro-strain has been successfully resolved from the silicon CTE extraction measurements. Furthermore, the spatial resolution has been studied on predefined grating patterns, which are assembled to mimic the uneven strain distribution across the sample surface. A resolvable feature size of 10 µm has been achieved with an incident laser spot size of 50 µm in diameter.
In addition, the strain sensing technique has been applied to a composite sample made of SU8 and silicon, as well as the microelectronic packages for thermal strain mappings.
The developed highly sensitive micro-strain sensing technique differs from the existing strain mapping techniques, such as digital image correlation (DIC)/micro-Moiré techniques, in terms of working mechanism, by filling a technology gap that requires high spatial resolution while simultaneously maintaining a large field-of-view. The strain sensing mechanism relies on the scanning of a tightly focused laser beam onto the grating that is on the sample surface to detect the change in the diffracted beam angle as a result of the strain. Gratings are fabricated on the target substrates to serve as strain sensors, which carries the strain information in the form of variations in the grating period. The geometric structure of the optical system inherently ensures the high sensitivity for the strain sensing, where the nanoscale change of the grating period is amplified by almost six orders into a diffraction peak shift on the order of several hundred micrometers. It significantly amplifies the small signal measurements so that the desired sensitivity and accuracy can be achieved.
The important features, such as strain sensitivity and spatial resolution, for the strain sensing technique are investigated to evaluate the technique. The strain sensitivity has been validated by measurements on homogenous materials with well known reference values of CTE (coefficient of thermal expansion). 10 micro-strain has been successfully resolved from the silicon CTE extraction measurements. Furthermore, the spatial resolution has been studied on predefined grating patterns, which are assembled to mimic the uneven strain distribution across the sample surface. A resolvable feature size of 10 µm has been achieved with an incident laser spot size of 50 µm in diameter.
In addition, the strain sensing technique has been applied to a composite sample made of SU8 and silicon, as well as the microelectronic packages for thermal strain mappings.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Poon, Poh Chieh Benny (Committee member) / Jiang, Hanqing (Committee member) / Zhang, Yong-Hang (Committee member) / Arizona State University (Publisher)
Created2014
Description
From 2D planar MOSFET to 3D FinFET, the geometry of semiconductor devices is getting more and more complex. Correspondingly, the number of mesh grid points increases largely to maintain the accuracy of carrier transport and heat transfer simulations. By substituting the conventional uniform mesh with non-uniform mesh, one can reduce the number of grid points. However, the problem of how to solve governing equations on non-uniform mesh is then imposed to the numerical solver. Moreover, if a device simulator is integrated into a multi-scale simulator, the problem size will be further increased. Consequently, there exist two challenges for the current numerical solver. One is to increase the functionality to accommodate non-uniform mesh. The other is to solve governing physical equations fast and accurately on a large number of mesh grid points.
This research rst discusses a 2D planar MOSFET simulator and its numerical solver, pointing out its performance limit. By analyzing the algorithm complexity, Multigrid method is proposed to replace conventional Successive-Over-Relaxation method in a numerical solver. A variety of Multigrid methods (standard Multigrid, Algebraic Multigrid, Full Approximation Scheme, and Full Multigrid) are discussed and implemented. Their properties are examined through a set of numerical experiments. Finally, Algebraic Multigrid, Full Approximation Scheme and Full Multigrid are integrated into one advanced numerical solver based on the exact requirements of a semiconductor device simulator. A 2D MOSFET device is used to benchmark the performance, showing that the advanced Multigrid method has higher speed, accuracy and robustness.
This research rst discusses a 2D planar MOSFET simulator and its numerical solver, pointing out its performance limit. By analyzing the algorithm complexity, Multigrid method is proposed to replace conventional Successive-Over-Relaxation method in a numerical solver. A variety of Multigrid methods (standard Multigrid, Algebraic Multigrid, Full Approximation Scheme, and Full Multigrid) are discussed and implemented. Their properties are examined through a set of numerical experiments. Finally, Algebraic Multigrid, Full Approximation Scheme and Full Multigrid are integrated into one advanced numerical solver based on the exact requirements of a semiconductor device simulator. A 2D MOSFET device is used to benchmark the performance, showing that the advanced Multigrid method has higher speed, accuracy and robustness.
ContributorsGuo, Xinchen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Ferry, David (Committee member) / Arizona State University (Publisher)
Created2015
Description
CMOS Technology has been scaled down to 7 nm with FinFET replacing planar MOSFET devices. Due to short channel effects, the FinFET structure was developed to provide better electrostatic control on subthreshold leakage and saturation current over planar MOSFETs while having the desired current drive. The FinFET structure has an undoped or fully depleted fin, which supports immunity from random dopant fluctuations (RDF – a phenomenon which causes a reduction in the threshold voltage and is prominent at sub 50 nm tech nodes due to lesser dopant atoms) and thus causes threshold voltage (Vth) roll-off by reducing the Vth. However, as the advanced CMOS technologies are shrinking down to a 5 nm technology node, subthreshold leakage and drain-induced-barrier-lowering (DIBL) are driving the introduction of new metal-oxide-semiconductor field-effect transistor (MOSFET) structures to improve performance. GAA field effect transistors are shown to be the potential candidates for these advanced nodes. In nanowire devices, due to the presence of the gate on all sides of the channel, DIBL should be lower compared to the FinFETs.
A 3-D technology computer aided design (TCAD) device simulation is done to compare the performance of FinFET and GAA nanowire structures with vertically stacked horizontal nanowires. Subthreshold slope, DIBL & saturation current are measured and compared between these devices. The FinFET’s device performance has been matched with the ASAP7 compact model with the impact of tensile and compressive strain on NMOS & PMOS respectively. Metal work function is adjusted for the desired current drive. The nanowires have shown better electrostatic performance over FinFETs with excellent improvement in DIBL and subthreshold slope. This proves that horizontal nanowires can be the potential candidate for 5 nm technology node. A GAA nanowire structure for 5 nm tech node is characterized with a gate length of 15 nm. The structure is scaled down from 7 nm node to 5 nm by using a scaling factor of 0.7.
A 3-D technology computer aided design (TCAD) device simulation is done to compare the performance of FinFET and GAA nanowire structures with vertically stacked horizontal nanowires. Subthreshold slope, DIBL & saturation current are measured and compared between these devices. The FinFET’s device performance has been matched with the ASAP7 compact model with the impact of tensile and compressive strain on NMOS & PMOS respectively. Metal work function is adjusted for the desired current drive. The nanowires have shown better electrostatic performance over FinFETs with excellent improvement in DIBL and subthreshold slope. This proves that horizontal nanowires can be the potential candidate for 5 nm technology node. A GAA nanowire structure for 5 nm tech node is characterized with a gate length of 15 nm. The structure is scaled down from 7 nm node to 5 nm by using a scaling factor of 0.7.
ContributorsRana, Parshant (Author) / Clark, Lawrence (Thesis advisor) / Ferry, David (Committee member) / Brunhaver, John (Committee member) / Arizona State University (Publisher)
Created2017
Description
Scaling of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) towards shorter channel lengths, has lead to an increasing importance of quantum effects on the device performance. Until now, a semi-classical model based on Monte Carlo method for instance, has been sufficient to address these issues in silicon, and arrive at a reasonably good fit to experimental mobility data. But as the semiconductor world moves towards 10nm technology, many of the basic assumptions in this method, namely the very fundamental Fermi’s golden rule come into question. The derivation of the Fermi’s golden rule assumes that the scattering is infrequent (therefore the long time limit) and the collision duration time is zero. This thesis overcomes some of the limitations of the above approach by successfully developing a quantum mechanical simulator that can model the low-field inversion layer mobility in silicon MOS capacitors and other inversion layers as well. It solves for the scattering induced collisional broadening of the states by accounting for the various scattering mechanisms present in silicon through the non-equilibrium based near-equilibrium Green’s Functions approach, which shall be referred to as near-equilibrium Green’s Function (nEGF) in this work. It adopts a two-loop approach, where the outer loop solves for the self-consistency between the potential and the subband sheet charge density by solving the Poisson and the Schrödinger equations self-consistently. The inner loop solves for the nEGF (renormalization of the spectrum and the broadening of the states), self-consistently using the self-consistent Born approximation, which is then used to compute the mobility using the Green-Kubo Formalism.
ContributorsJayaram Thulasingam, Gokula Kannan (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2017