Matching Items (46)
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- All Subjects: Electrical Engineering
- Creators: Barnaby, Hugh
- Status: Published
Description
In recent years, the Silicon Super-Junction (SJ) power metal-oxide semiconductor field-effect transistor (MOSFET), has garnered significant interest from spacecraft designers. This is due to their high breakdown voltage and low specific on-state resistance characteristics. Most of the previous research work on power MOSFETS for space applications concentrated on improving the radiation tolerance of low to medium voltage (~ 300V) power MOSFETs. Therefore, understanding and improving the reliability of high voltage SJMOS for the harsh space radiation environment is an important endeavor.In this work, a 600V commercially available silicon planar gate SJMOS is used to study the SJ technology’s tolerance against total ionizing dose (TID) and destructive single event effects (SEE), such as, single event burnout (SEB) and single event gate rupture (SEGR). A technology computer aided design (TCAD) software tool is used to design the SJMOS and simulate its electrical characteristics.
Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide
itride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide
itride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors.
Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance.
Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide
itride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide
itride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors.
Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance.
ContributorsMuthuseenu, Kiraneswar (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Holbert, Keith E. (Committee member) / Gonzalez Velo, Yago (Committee member) / Arizona State University (Publisher)
Created2020
Description
Lateral programmable metallization cells (PMC) utilize the properties of electrodeposits grown over a solid electrolyte channel. Such devices have an active anode and an inert cathode separated by a long electrodeposit channel in a coplanar arrangement. The ability to transport large amount of metallic mass across the channel makes these devices attractive for various More-Than-Moore applications. Existing literature lacks a comprehensive study of electrodeposit growth kinetics in lateral PMCs. Moreover, the morphology of electrodeposit growth in larger, planar devices is also not understood. Despite the variety of applications, lateral PMCs are not embraced by the semiconductor industry due to incompatible materials and high operating voltages needed for such devices. In this work, a numerical model based on the basic processes in PMCs – cation drift and redox reactions – is proposed, and the effect of various materials parameters on the electrodeposit growth kinetics is reported. The morphology of the electrodeposit growth and kinetics of the electrodeposition process are also studied in devices based on Ag-Ge30Se70 materials system. It was observed that the electrodeposition process mainly consists of two regimes of growth – cation drift limited regime and mixed regime. The electrodeposition starts in cation drift limited regime at low electric fields and transitions into mixed regime as the field increases. The onset of mixed regime can be controlled by applied voltage which also affects the morphology of electrodeposit growth. The numerical model was then used to successfully predict the device kinetics and onset of mixed regime. The problem of materials incompatibility with semiconductor manufacturing was solved by proposing a novel device structure. A bilayer structure using semiconductor foundry friendly materials was suggested as a candidate for solid electrolyte. The bilayer structure consists of a low resistivity oxide shunt layer on top of a high resistivity ion carrying oxide layer. Devices using Cu2O as the low resistivity shunt on top of Cu doped WO3 oxide were fabricated. The bilayer devices provided orders of magnitude improvement in device performance in the context of operating voltage and switching time. Electrical and materials characterization revealed the structure of bilayers and the mechanism of electrodeposition in these devices.
ContributorsChamele, Ninad (Author) / Kozicki, Michael (Thesis advisor) / Barnaby, Hugh (Committee member) / Newman, Nathan (Committee member) / Gonzalez-Velo, Yago (Committee member) / Arizona State University (Publisher)
Created2020
Description
Most hardware today is based on von Neumann architecture separating memory from logic. Valuable processing time is lost in shuttling information back and forth between the two units, a problem called von Neumann bottleneck. As transistors are scaled further down, this bottleneck will make it harder to deliver performance in computing power. Adding to this is the increasing complexity of artificial intelligence logic. Thus, there is a need for a faster and more efficient method of computing. Neuromorphic systems deliver this by emulating the massively parallel and fault-tolerant computing capabilities of the human brain where the action potential is triggered by multiple inputs at once (spatial) or an input that builds up over time (temporal). Highly scalable memristors are key in these systems- they can maintain their internal resistive state based on previous current/voltage values thus mimicking the way the strength of two synapses in the brain can vary. The brain-inspired algorithms are implemented by vector matrix multiplications (VMMs) to provide neuronal outputs. High-density conductive bridging random access memory (CBRAM) crossbar arrays (CBAs) can perform VMMs parallelly with ultra-low energy.This research explores a simple planarization technique that could be potentially extended to integrate front-end-of-line (FEOL) processing of complementary metal oxide semiconductor (CMOS) circuitry with back-end-of-line (BEOL) processing of CBRAM CBAs for one-transistor one-resistor (1T1R) Neuromorphic CMOS chips where the transistor is part of the CMOS circuitry and the CBRAM forms the resistor. It is a photoresist (PR) and spin-on glass (SOG) based planarization recipe to planarize CBRAM electrode patterns on a silicon substrate. In this research, however, the planarization is only applied to mechanical grade (MG) silicon wafers without any CMOS layers on them. The planarization achieved was of a very high order (few tens of nanometers). Additionally, the recipe is cost-effective, provides good quality films and simple as only two types of process technologies are involved- lithography and dry etching.
Subsequent processing would involve depositing the CBRAM layers onto the planarized electrodes to form the resistor. Finally, the entire process flow is to be replicated onto wafers with CMOS layers to form the 1T1R circuit.
ContributorsBiswas, Prabaha (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Velo, Yago Gonzalez (Committee member) / Arizona State University (Publisher)
Created2021
Description
Analog to Digital Converters (ADCs) are a critical component in modern circuit applications. ADCs are used in virtually every application in which a digital circuit is interacting with data from the real world, ranging from commercial applications to crucial military and aerospace applications, and are especially important when interacting with sensors that observe environmental factors. Due to the critical nature of these converters, as well as the vast range of environments in which they are used, it is important that they accurately sample data regardless of environmental factors. These environmental factors range from input noise and power supply variations to temperature and radiation, and it is important to know how each may affect the accuracy of the resulting data when designing circuits that depend upon the data from these ADCs. These environmental factors are considered hostile environments, as they each generally have a negative effect on the operation of an ADC. This thesis seeks to investigate the effects of several of these hostile environmental variables on the performance of analog to digital converters. Three different analog to digital converters with similar specifications were selected and analyzed under common hostile environments. Data was collected on multiple copies of an ADC and averaged together to analyze the results using multiple characteristics of converter performance. Performance metrics were obtained across a range of frequencies, input noise, input signal offsets, power supply voltages, and temperatures. The obtained results showed a clear decrease in performance farther from a room temperature environment, but the results for several other environmental variables showed either no significant correlation or resulted in inconclusive data.
ContributorsSwanson, Taylor Catherine (Co-author) / Millman, Hershel (Co-author) / Barnaby, Hugh (Thesis director) / Garrity, Douglas (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2019-05
Description
ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR and hence the maximum resolution that can be achieved by ADC. With the RSD algorithm and the range overlap, the sub ADC can tolerate large comparator offsets leaving the linearity and accuracy requirement for the DAC and residue gain stage. Typically, the multiplying DAC requires high gain wide bandwidth op-amp and the design of this high gain op-amp becomes challenging in the deep submicron technologies. This work presents `A 12 bit 25MSPS 1.2V pipelined ADC using split CLS technique' in IBM 130nm 8HP process using only CMOS devices for the application of Large Hadron Collider (LHC). CLS technique relaxes the gain requirement of op-amp and improves the signal-to-noise ratio without increase in power or input sampling capacitor with rail-to-rail swing. An op-amp sharing technique has been incorporated with split CLS technique which decreases the number of op-amps and hence the power further. Entire pipelined converter has been implemented as six 2.5 bit RSD stages and hence decreases the latency associated with the pipelined architecture - one of the main requirements for LHC along with the power requirement. Two different OTAs have been designed to use in the split-CLS technique. Bootstrap switches and pass gate switches are used in the circuit along with a low power dynamic kick-back compensated comparator.
ContributorsSwaminathan, Visu Vaithiyanathan (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
Machine learning advancements have led to increasingly complex algorithms, resulting in significant energy consumption due to heightened memory-transfer requirements and inefficient vector matrix multiplication (VMM). To address this issue, many have proposed ReRAM analog in-memory computing (AIMC) as a solution. AIMC enhances the time-energy efficiency of VMM operations beyond conventional VMM digital hardware, such as a tensor processing unit (TPU), while substantially reducing memory-transfer demands through in-memory computing. As AIMC gains prominence as a solution, it becomes crucial to optimize ReRAM and analog crossbar architecture characteristics. This thesis introduces an application-specific integrated circuit (ASIC) tailored forcharacterizing ReRAM within a crossbar array architecture and discusses the interfacing techniques employed. It discusses ReRAM forming and programming techniques and showcases chip’s ability to utilize the write-verify programming method to write image pixels on a conductance heat map. Additionally, this thesis assesses the ASIC’s capability to characterize different aspects of ReRAM, including drift and noise characteristics. The research employs the chip to extract ReRAM data and models it within a crossbar array simulator, enabling its application in the classification of the CIFAR-10 dataset.
ContributorsShort, Jesse (Author) / Marinella, Matthew (Thesis advisor) / Barnaby, Hugh (Committee member) / Sanchez Esqueda, Ivan (Committee member) / Arizona State University (Publisher)
Created2023