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Description
This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.
ContributorsMahalanabis, Debayan (Author) / Barnaby, Hugh J. (Thesis advisor) / Kozicki, Michael N. (Committee member) / Vrudhula, Sarma (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2015
Description
Internet of Things (IoT) has become a popular topic in industry over the recent years, which describes an ecosystem of internet-connected devices or things that enrich the everyday life by improving our productivity and efficiency. The primary components of the IoT ecosystem are hardware, software and services. While the software and services of IoT system focus on data collection and processing to make decisions, the underlying hardware is responsible for sensing the information, preprocess and transmit it to the servers. Since the IoT ecosystem is still in infancy, there is a great need for rapid prototyping platforms that would help accelerate the hardware design process. However, depending on the target IoT application, different sensors are required to sense the signals such as heart-rate, temperature, pressure, acceleration, etc., and there is a great need for reconfigurable platforms that can prototype different sensor interfacing circuits.
This thesis primarily focuses on two important hardware aspects of an IoT system: (a) an FPAA based reconfigurable sensing front-end system and (b) an FPGA based reconfigurable processing system. To enable reconfiguration capability for any sensor type, Programmable ANalog Device Array (PANDA), a transistor-level analog reconfigurable platform is proposed. CAD tools required for implementation of front-end circuits on the platform are also developed. To demonstrate the capability of the platform on silicon, a small-scale array of 24×25 PANDA cells is fabricated in 65nm technology. Several analog circuit building blocks including amplifiers, bias circuits and filters are prototyped on the platform, which demonstrates the effectiveness of the platform for rapid prototyping IoT sensor interfaces.
IoT systems typically use machine learning algorithms that run on the servers to process the data in order to make decisions. Recently, embedded processors are being used to preprocess the data at the energy-constrained sensor node or at IoT gateway, which saves considerable energy for transmission and bandwidth. Using conventional CPU based systems for implementing the machine learning algorithms is not energy-efficient. Hence an FPGA based hardware accelerator is proposed and an optimization methodology is developed to maximize throughput of any convolutional neural network (CNN) based machine learning algorithm on a resource-constrained FPGA.
This thesis primarily focuses on two important hardware aspects of an IoT system: (a) an FPAA based reconfigurable sensing front-end system and (b) an FPGA based reconfigurable processing system. To enable reconfiguration capability for any sensor type, Programmable ANalog Device Array (PANDA), a transistor-level analog reconfigurable platform is proposed. CAD tools required for implementation of front-end circuits on the platform are also developed. To demonstrate the capability of the platform on silicon, a small-scale array of 24×25 PANDA cells is fabricated in 65nm technology. Several analog circuit building blocks including amplifiers, bias circuits and filters are prototyped on the platform, which demonstrates the effectiveness of the platform for rapid prototyping IoT sensor interfaces.
IoT systems typically use machine learning algorithms that run on the servers to process the data in order to make decisions. Recently, embedded processors are being used to preprocess the data at the energy-constrained sensor node or at IoT gateway, which saves considerable energy for transmission and bandwidth. Using conventional CPU based systems for implementing the machine learning algorithms is not energy-efficient. Hence an FPGA based hardware accelerator is proposed and an optimization methodology is developed to maximize throughput of any convolutional neural network (CNN) based machine learning algorithm on a resource-constrained FPGA.
ContributorsSuda, Naveen (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Yu, Shimeng (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016
Description
Solid-state nanopore research, used in the field of biomolecule detection and separation, has developed rapidly during the last decade. An electric field generated from the nanopore membrane to the aperture surface by a bias voltage can be used to electrostatically control the transport of charges. This results in ionic current rectification that can be used for applications such as biomolecule filtration and DNA sequencing.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
ContributorsWang, Xiaofeng (Author) / Goryll, Michael (Thesis advisor) / Thornton, Trevor J (Committee member) / Christen, Jennifer M (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015
Description
A novel integrated constant current LED driver design on a single chip is developed in this dissertation. The entire design consists of two sections. The first section is a DC-DC switching regulator (boost regulator) as the frontend power supply; the second section is the constant current LED driver system.
In the first section, a pulse width modulated (PWM) peak current mode boost regulator is utilized. The overall boost regulator system and its related sub-cells are explained. Among them, an original error amplifier design, a current sensing circuit and slope compensation circuit are presented.
In the second section – the focus of this dissertation – a highly accurate constant current LED driver system design is unveiled. The detailed description of this highly accurate LED driver system and its related sub-cells are presented. A hybrid PWM and linear current modulation scheme to adjust the LED driver output currents is explained. The novel design ideas to improve the LED current accuracy and channel-to-channel output current mismatch are also explained in detail. These ideas include a novel LED driver system architecture utilizing 1) a dynamic current mirror structure and 2) a closed loop structure to keep the feedback loop of the LED driver active all the time during both PWM on-duty and PWM off-duty periods. Inside the LED driver structure, the driving amplifier with a novel slew rate enhancement circuit to dramatically accelerate its response time is also presented.
In the first section, a pulse width modulated (PWM) peak current mode boost regulator is utilized. The overall boost regulator system and its related sub-cells are explained. Among them, an original error amplifier design, a current sensing circuit and slope compensation circuit are presented.
In the second section – the focus of this dissertation – a highly accurate constant current LED driver system design is unveiled. The detailed description of this highly accurate LED driver system and its related sub-cells are presented. A hybrid PWM and linear current modulation scheme to adjust the LED driver output currents is explained. The novel design ideas to improve the LED current accuracy and channel-to-channel output current mismatch are also explained in detail. These ideas include a novel LED driver system architecture utilizing 1) a dynamic current mirror structure and 2) a closed loop structure to keep the feedback loop of the LED driver active all the time during both PWM on-duty and PWM off-duty periods. Inside the LED driver structure, the driving amplifier with a novel slew rate enhancement circuit to dramatically accelerate its response time is also presented.
ContributorsWang, Ge (Author) / Holbert, Keith E. (Thesis advisor) / Song, Hongjiang (Committee member) / Ayyanar, Raja (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2016
Towards high-efficiency thin-film solar cells: from theoretical analysis to experimental exploration
Description
GaAs single-junction solar cells have been studied extensively in recent years, and have reached over 28 % efficiency. Further improvement requires an optically thick but physically thin absorber to provide both large short-circuit current and high open-circuit voltage. By detailed simulation, it is concluded that ultra-thin GaAs cells with hundreds of nanometers thickness and reflective back scattering can potentially offer efficiencies greater than 30 %. The 300 nm GaAs solar cell with AlInP/Au reflective back scattering is carefully designed and demonstrates an efficiency of 19.1 %. The device performance is analyzed using the semi-analytical model with Phong distribution implemented to account for non-Lambertian scattering. A Phong exponent m of ~12, a non-radiative lifetime of 130 ns, and a specific series resistivity of 1.2 Ω·cm2 are determined.
Thin-film CdTe solar cells have also attracted lots of attention due to the continuous improvements in their device performance. To address the issue of the lower efficiency record compared to detailed-balance limit, the single-crystalline Cd(Zn)Te/MgCdTe double heterostructures (DH) grown on InSb (100) substrates by molecular beam epitaxy (MBE) are carefully studied. The Cd0.9946Zn0.0054Te alloy lattice-matched to InSb has been demonstrated with a carrier lifetime of 0.34 µs observed in a 3 µm thick Cd0.9946Zn0.0054Te/MgCdTe DH sample. The substantial improvement of lifetime is due to the reduction in misfit dislocation density. The recombination lifetime and interface recombination velocity (IRV) of CdTe/MgxCd1-xTe DHs are investigated. The IRV is found to be dependent on both the MgCdTe barrier height and width due to the thermionic emission and tunneling processes. A record-long carrier lifetime of 2.7 µs and a record-low IRV of close to zero have been confirmed experimentally.
The MgCdTe/Si tandem solar cell is proposed to address the issue of high manufacturing costs and poor performance of thin-film solar cells. The MBE grown MgxCd1-xTe/MgyCd1-yTe DHs have demonstrated the required bandgap energy of 1.7 eV, a carrier lifetime of 11 ns, and an effective IRV of (1.869 ± 0.007) × 103 cm/s. The large IRV is attributed to thermionic-emission induced interface recombination. These understandings can be applied to fabricating the high-efficiency low-cost MgCdTe/Si tandem solar cell.
Thin-film CdTe solar cells have also attracted lots of attention due to the continuous improvements in their device performance. To address the issue of the lower efficiency record compared to detailed-balance limit, the single-crystalline Cd(Zn)Te/MgCdTe double heterostructures (DH) grown on InSb (100) substrates by molecular beam epitaxy (MBE) are carefully studied. The Cd0.9946Zn0.0054Te alloy lattice-matched to InSb has been demonstrated with a carrier lifetime of 0.34 µs observed in a 3 µm thick Cd0.9946Zn0.0054Te/MgCdTe DH sample. The substantial improvement of lifetime is due to the reduction in misfit dislocation density. The recombination lifetime and interface recombination velocity (IRV) of CdTe/MgxCd1-xTe DHs are investigated. The IRV is found to be dependent on both the MgCdTe barrier height and width due to the thermionic emission and tunneling processes. A record-long carrier lifetime of 2.7 µs and a record-low IRV of close to zero have been confirmed experimentally.
The MgCdTe/Si tandem solar cell is proposed to address the issue of high manufacturing costs and poor performance of thin-film solar cells. The MBE grown MgxCd1-xTe/MgyCd1-yTe DHs have demonstrated the required bandgap energy of 1.7 eV, a carrier lifetime of 11 ns, and an effective IRV of (1.869 ± 0.007) × 103 cm/s. The large IRV is attributed to thermionic-emission induced interface recombination. These understandings can be applied to fabricating the high-efficiency low-cost MgCdTe/Si tandem solar cell.
ContributorsLiu, Shi (Author) / Zhang, Yong-Hang (Thesis advisor) / Johnson, Shane R (Committee member) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015
Description
The microelectronics technology has seen a tremendous growth over the past sixty years. The advancements in microelectronics, which shows the capability of yielding highly reliable and reproducible structures, have made the mass production of integrated electronic components feasible. Miniaturized, low-cost, and accurate sensors became available due to the rise of the microelectronics industry. A variety of sensors are being used extensively in many portable applications. These sensors are promising not only in research area but also in daily routine applications.
However, many sensing systems are relatively bulky, complicated, and expensive and main advantages of new sensors do not play an important role in practical applications. Many challenges arise due to intricacies for sensor packaging, especially operation in a solution environment. Additional problems emerge when interfacing sensors with external off-chip components. A large amount of research in the field of sensors has been focused on how to improve the system integration.
This work presents new methods for the design, fabrication, and integration of sensor systems. This thesis addresses these challenges, for example, interfacing microelectronic system to a liquid environment and developing a new technique for impedimetric measurement. This work also shows a new design for on-chip optical sensor without any other extra components or post-processing.
However, many sensing systems are relatively bulky, complicated, and expensive and main advantages of new sensors do not play an important role in practical applications. Many challenges arise due to intricacies for sensor packaging, especially operation in a solution environment. Additional problems emerge when interfacing sensors with external off-chip components. A large amount of research in the field of sensors has been focused on how to improve the system integration.
This work presents new methods for the design, fabrication, and integration of sensor systems. This thesis addresses these challenges, for example, interfacing microelectronic system to a liquid environment and developing a new technique for impedimetric measurement. This work also shows a new design for on-chip optical sensor without any other extra components or post-processing.
ContributorsLuo, Tao (Author) / Blain Christen, Jennifer (Thesis advisor) / Song, Hongjiang (Committee member) / Goryll, Michael (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015
Description
Electromagnetic band-gap (EBG) structures have noteworthy electromagnetic characteristics that include their phase variations with frequency. When combining perfect electric conductor (PEC) and EBG structures on the same ground plane, the scattering fields of the ground plane are altered because of the scattering properties of EBG structures. The scattering fields are cancelled along the principal planes because PEC and EBG structures are anti-phase at the resonant frequency. To make the scattered fields symmetrical under plane wave incidence, a square checkerboard surface is designed to form constructive and destructive interference scattering patterns to reduce the intensity of the scattered fields toward the observer; thus reducing the radar cross section (RCS). To increase the 10-dB RCS reduction (compared to a PEC surface) bandwidth, checkerboard surfaces of two different EBG structures on the same ground plane are designed. Thus, significant RCS reduction over a wider frequency bandwidth of about 63% is achieved.
Another design is a hexagonal checkerboard surface that achieves the same RCS reduction bandwidth because it combines the same EBG designs. The hexagonal checkerboard design further reduce the RCS than square checkerboard designs because the reflected energy is re-directed toward six directions and a null remains in the normal direction.
A dual frequency band checkerboard surface with 10-dB RCS reduction bandwidths of 61% and 24% is realized by utilizing two dual-band EBG structures, while the surfaces maintain scattering in four quadrants. The first RCS reduction bandwidth of the dual band is basically the same as in the square checkerboard design; however, the present surface exhibits a second frequency band of 10-dB RCS reduction.
Finally, cylindrically curved checkerboard surfaces are designed and examined for three different radii of curvature. Both narrow and wide band curved checkerboard surfaces are evaluated under normal incidence for both horizontal and vertical polarizations. Simulated bistatic RCS patterns of the cylindrical checkerboard surfaces are presented.
For all designs, bistatic and monostatic RCS of each checkerboard surface design are compared to that of the corresponding PEC surface. The monostatic simulations are also compared with measurements as a function of frequency and polarization. A very good agreement has been attained throughout.
Another design is a hexagonal checkerboard surface that achieves the same RCS reduction bandwidth because it combines the same EBG designs. The hexagonal checkerboard design further reduce the RCS than square checkerboard designs because the reflected energy is re-directed toward six directions and a null remains in the normal direction.
A dual frequency band checkerboard surface with 10-dB RCS reduction bandwidths of 61% and 24% is realized by utilizing two dual-band EBG structures, while the surfaces maintain scattering in four quadrants. The first RCS reduction bandwidth of the dual band is basically the same as in the square checkerboard design; however, the present surface exhibits a second frequency band of 10-dB RCS reduction.
Finally, cylindrically curved checkerboard surfaces are designed and examined for three different radii of curvature. Both narrow and wide band curved checkerboard surfaces are evaluated under normal incidence for both horizontal and vertical polarizations. Simulated bistatic RCS patterns of the cylindrical checkerboard surfaces are presented.
For all designs, bistatic and monostatic RCS of each checkerboard surface design are compared to that of the corresponding PEC surface. The monostatic simulations are also compared with measurements as a function of frequency and polarization. A very good agreement has been attained throughout.
ContributorsChen, Wengang (Author) / Balanis, Constantine A. (Thesis advisor) / Aberle, James T. (Committee member) / Yu, Hongbin (Committee member) / Palais, Joseph C. (Committee member) / Arizona State University (Publisher)
Created2016
Description
Nanowires are one-dimensional (1D) structures with diameter on the nanometer scales with a high length-to-diameter aspect ratio. Nanowires of various materials including semiconductors, dielectrics and metals have been intensively researched in the past two decades for applications to electrical and optical devices. Typically, nanowires are synthesized using the vapor-liquid-solid (VLS) approach, which allows defect-free 1D growth despite the lattice mismatch between nanowires and substrates. Lattice mismatch issue is a serious problem in high-quality thin film growth of many semiconductors and non-semiconductors. Therefore, nanowires provide promising platforms for the applications requiring high crystal quality materials.
With the 1D geometry, nanowires are natural optical waveguides for light guiding and propagation. By introducing feedback mechanisms to nanowire waveguides, such as the cleaved end facets, the nanowires can work as ultra-small size lasers. Since the first demonstration of the room-temperature ultraviolet nanowire lasers in 2001, the nanowire lasers covering from ultraviolet to mid infrared wavelength ranges have been intensively studied. This dissertation focuses on the optical characterization and laser fabrication of two nanowire materials: erbium chloride silicate nanowires and composition-graded CdSSe semiconductor alloy nanowires.
Chapter 1 – 5 of this dissertation presents a comprehensive characterization of a newly developed erbium compound material, erbium chloride silicate (ECS) in a nanowire form. Extensive experiments demonstrated the high crystal quality and excellent optical properties of ECS nanowires. Optical gain higher than 30 dB/cm at 1.53 μm wavelength is demonstrated on single ECS nanowires, which is higher than the gain of any reported erbium materials. An ultra-high Q photonic crystal micro-cavity is designed on a single ECS nanowire towards the ultra-compact lasers at communication wavelengths. Such ECS nanowire lasers show the potential applications of on-chip photonics integration.
Chapter 6 – 7 presents the design and demonstration of dynamical color-controllable lasers on a single CdSSe alloy nanowire. Through the defect-free VLS growth, engineering of the alloy composition in a single nanowire is achieved. The alloy composition of CdSxSe1-x uniformly varies along the nanowire axis from x=1 to x=0, giving the opportunity of multi-color lasing in a monolithic structure. By looping the wide-bandgap end of the alloy nanowire through nanoscale manipulation, the simultaneous two-color lasing at green and red colors are demonstrated. The 107 nm wavelength separation of the two lasing colors is much larger than the gain bandwidth of typical semiconductors. Since the two-color lasing shares the output port, the color of the total lasing output can be controlled dynamically between the two fundamental colors by changing the relative output power of two lasing colors. Such multi-color lasing and continuous color tuning in a wide spectral range would eventually enable color-by-design lasers to be used for lighting, display and many other applications.
With the 1D geometry, nanowires are natural optical waveguides for light guiding and propagation. By introducing feedback mechanisms to nanowire waveguides, such as the cleaved end facets, the nanowires can work as ultra-small size lasers. Since the first demonstration of the room-temperature ultraviolet nanowire lasers in 2001, the nanowire lasers covering from ultraviolet to mid infrared wavelength ranges have been intensively studied. This dissertation focuses on the optical characterization and laser fabrication of two nanowire materials: erbium chloride silicate nanowires and composition-graded CdSSe semiconductor alloy nanowires.
Chapter 1 – 5 of this dissertation presents a comprehensive characterization of a newly developed erbium compound material, erbium chloride silicate (ECS) in a nanowire form. Extensive experiments demonstrated the high crystal quality and excellent optical properties of ECS nanowires. Optical gain higher than 30 dB/cm at 1.53 μm wavelength is demonstrated on single ECS nanowires, which is higher than the gain of any reported erbium materials. An ultra-high Q photonic crystal micro-cavity is designed on a single ECS nanowire towards the ultra-compact lasers at communication wavelengths. Such ECS nanowire lasers show the potential applications of on-chip photonics integration.
Chapter 6 – 7 presents the design and demonstration of dynamical color-controllable lasers on a single CdSSe alloy nanowire. Through the defect-free VLS growth, engineering of the alloy composition in a single nanowire is achieved. The alloy composition of CdSxSe1-x uniformly varies along the nanowire axis from x=1 to x=0, giving the opportunity of multi-color lasing in a monolithic structure. By looping the wide-bandgap end of the alloy nanowire through nanoscale manipulation, the simultaneous two-color lasing at green and red colors are demonstrated. The 107 nm wavelength separation of the two lasing colors is much larger than the gain bandwidth of typical semiconductors. Since the two-color lasing shares the output port, the color of the total lasing output can be controlled dynamically between the two fundamental colors by changing the relative output power of two lasing colors. Such multi-color lasing and continuous color tuning in a wide spectral range would eventually enable color-by-design lasers to be used for lighting, display and many other applications.
ContributorsLiu, Zhicheng (Author) / Ning, Cun-Zheng (Thesis advisor) / Palais, Joseph (Committee member) / Yu, Hongbin (Committee member) / Yao, Yu (Committee member) / Arizona State University (Publisher)
Created2015
Description
Semiconductor nanowires are important candidates for highly scaled three dimensional electronic devices. It is very advantageous to combine their scaling capability with the high yield of planar CMOS technology by integrating nanowire devices into planar circuits. The purpose of this research is to identify the challenges associated with the fabrication of vertically oriented Si and Ge nanowire diodes and modeling their electrical behavior so that they can be utilized to create unique three dimensional architectures that can boost the scaling of electronic devices into the next generation. In this study, vertical Ge and Si nanowire Schottky diodes have been fabricated using bottom-up vapor-liquid-solid (VLS) and top-down reactive ion etching (RIE) approaches respectively. VLS growth yields nanowires with atomically smooth sidewalls at sub-50 nm diameters but suffers from the problem that the doping increases radially outwards from the core of the devices. RIE is much faster than VLS and does not suffer from the problem of non-uniform doping. However, it yields nanowires with rougher sidewalls and gets exceedingly inefficient in yielding vertical nanowires for diameters below 50 nm. The I-V characteristics of both Ge and Si nanowire diodes cannot be adequately fit by the thermionic emission model. Annealing in forming gas which passivates dangling bonds on the nanowire surface is shown to have a considerable impact on the current through the Si nanowire diodes indicating that fixed charges and traps on the surface of the devices play a major role in determining their electrical behavior. Also, due to the vertical geometry of the nanowire diodes, electric field lines originating from the metal and terminating on their sidewalls can directly modulate their conductivity. Both these effects have to be included in the model aimed at predicting the current through vertical nanowire diodes. This study shows that the current through vertical nanowire diodes cannot be predicted accurately using the thermionic emission model which is suitable for planar devices and identifies the factors needed to build a comprehensive analytical model for predicting the current through vertically oriented nanowire diodes.
ContributorsChandra, Nishant (Author) / Goodnick, Stephen M (Thesis advisor) / Tracy, Clarence J. (Committee member) / Yu, Hongbin (Committee member) / Ferry, David K. (Committee member) / Arizona State University (Publisher)
Created2014
Description
This thesis summarizes modeling and simulation of plasmonic waveguides and nanolasers. The research includes modeling of dielectric constants of doped semiconductor as a potential plasmonic material, simulation of plasmonic waveguides with different configurations and geometries, simulation and design of plasmonic nanolasers. In the doped semiconductor part, a more accurate model accounting for dielectric constant of doped InAs was proposed. In the model, Interband transitions accounted for by Adachi's model considering Burstein-Moss effect and free electron effect governed by Drude model dominate in different spectral regions. For plasmonic waveguide part, Insulator-Metal-Insulator (IMI) waveguide, silver nanowire waveguide with and without substrate, Metal-Semiconductor-Metal (MSM) waveguide and Metal-Insulator-Semiconductor-Insulator-Metal (MISIM) waveguide were investigated respectively. Modal analysis was given for each part. Lastly, a comparative study of plasmonic and optical modes in an MSM disk cavity was performed by FDTD simulation for room temperature at the telecommunication wavelength. The results show quantitatively that plasmonic modes have advantages over optical modes in the scalability down to small size and the cavity Quantum Electrodynamics(QED) effects due to the possibility of breaking the diffraction limit. Surprisingly for lasing characteristics, though plasmonic modes have large loss as expected, minimal achievable threshold can be attained for whispering gallery plasmonic modes with azimuthal number of 2 by optimizing cavity design at 1.55µm due to interplay of metal loss and radiation loss.
ContributorsWang, Haotong (Author) / Ning, Cunzheng (Thesis advisor) / Palais, Joseph (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2014