Matching Items (3)
Filtering by
- All Subjects: Electrical Engineering
- All Subjects: Non-volatile Memory
Description
Parents in STEM careers are more apt to guide their kids towards STEM careers (Sherburne-Michigan, 2017). There are STEM programs and classes for students who are interested in related fields, but the conundrum is that students need to be interested in order to choose to participate. The goal of this creative project was to introduce engineering concepts in a high school class to reveal and investigate the ways in which engineering concepts can be successfully introduced to a larger student populace to increase interest in engineering programs, courses, and degrees. A lesson plan and corresponding materials - including circuit kits and a simulated ball launching station with graphical display - were made to accomplish this goal. Throughout the lesson students were asked to (1) use given materials to accomplish a goal, (2) predict outcomes based on conceptual understanding and mathematical calculations, (3) test predictions, (4) record data, and (5) analyze data to generate results. The students first created a simple circuit to understand the circuit components and learn general electrical engineering concepts. A simple light dimmer circuit let students demonstrate understanding of electrical concepts (e.g., voltage, current resistance) before using the circuit to a simulated motor in order to launch a ball. The students were then asked to predict the time and height of a ball launched with various settings of their control circuit. The students were able to test their theories with the simulated launcher test set up shown in Figure 25 and collect data to create a parabolic height versus time graph. Based on the measured graph, the students were able to record their results and compare calculated values to real-world measured values. The results of the study suggest ways to introduce students to engineering while developing hands-on concept modeling of projectile motion and circuit design in math classrooms. Additionally, this lesson identifies a rich topic for teachers and STEM education researchers to explore lesson plans with interdisciplinary connections to engineering. This report will include the inspiration for the product, related work, iterative design process, and the final design. This information will be followed by user feedback, a project reflection, and lessons learned. The report will conclude with a summary and a discussion of future work.
ContributorsBurgess, Kylee Rae (Author) / Jordan, Shawn (Thesis director) / Sohoni, Sohum (Committee member) / Kinach, Barbara (Committee member) / Engineering Programs (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
As persistent non-volatile memory solutions become integrated in the computing ecosystem and landscape, traditional commodity file systems architected and developed for traditional block I/O based memory solutions must be reevaluated. A majority of commodity file systems have been architected and designed with the goal of managing data on non-volatile storage devices such as hard disk drives (HDDs) and solid state drives (SSDs). HDDs and SSDs are attached to a computing system via a controller or I/O hub, often referred to as the southbridge. The point of HDD and SSD attachment creates multiple levels of translation for any data managed by the CPU that must be stored in non-volatile memory (NVM) on an HDD or SSD. Storage Class Memory (SCM) devices provide the ability to store data at the CPU and DRAM level of a computing system. A novel set of modifications to the ext2 and ext4 commodity file systems to address the needs of SCM will be presented and discussed. An in-depth analysis of many existing file systems, from multiple sources, will be presented along with an analysis to identify key modifications and extensions that would be necessary to execute file system on SCM devices. From this analysis, modifications and extensions have been applied to the FAT commodity file system for key functional tests that will be presented to demonstrate the operation and execution of the file system extensions.
ContributorsRobles, Raymond (Author) / Syrotiuk, Violet (Thesis advisor) / Sohoni, Sohum (Committee member) / Wu, Carole-Jean (Committee member) / Arizona State University (Publisher)
Created2016
Description
The information era has brought about many technological advancements in the past
few decades, and that has led to an exponential increase in the creation of digital images and
videos. Constantly, all digital images go through some image processing algorithm for
various reasons like compression, transmission, storage, etc. There is data loss during this
process which leaves us with a degraded image. Hence, to ensure minimal degradation of
images, the requirement for quality assessment has become mandatory. Image Quality
Assessment (IQA) has been researched and developed over the last several decades to
predict the quality score in a manner that agrees with human judgments of quality. Modern
image quality assessment (IQA) algorithms are quite effective at prediction accuracy, and
their development has not focused on improving computational performance. The existing
serial implementation requires a relatively large run-time on the order of seconds for a single
frame. Hardware acceleration using Field programmable gate arrays (FPGAs) provides
reconfigurable computing fabric that can be tailored for a broad range of applications.
Usually, programming FPGAs has required expertise in hardware descriptive languages
(HDLs) or high-level synthesis (HLS) tool. OpenCL is an open standard for cross-platform,
parallel programming of heterogeneous systems along with Altera OpenCL SDK, enabling
developers to use FPGA's potential without extensive hardware knowledge. Hence, this
thesis focuses on accelerating the computationally intensive part of the most apparent
distortion (MAD) algorithm on FPGA using OpenCL. The results are compared with CPU
implementation to evaluate performance and efficiency gains.
few decades, and that has led to an exponential increase in the creation of digital images and
videos. Constantly, all digital images go through some image processing algorithm for
various reasons like compression, transmission, storage, etc. There is data loss during this
process which leaves us with a degraded image. Hence, to ensure minimal degradation of
images, the requirement for quality assessment has become mandatory. Image Quality
Assessment (IQA) has been researched and developed over the last several decades to
predict the quality score in a manner that agrees with human judgments of quality. Modern
image quality assessment (IQA) algorithms are quite effective at prediction accuracy, and
their development has not focused on improving computational performance. The existing
serial implementation requires a relatively large run-time on the order of seconds for a single
frame. Hardware acceleration using Field programmable gate arrays (FPGAs) provides
reconfigurable computing fabric that can be tailored for a broad range of applications.
Usually, programming FPGAs has required expertise in hardware descriptive languages
(HDLs) or high-level synthesis (HLS) tool. OpenCL is an open standard for cross-platform,
parallel programming of heterogeneous systems along with Altera OpenCL SDK, enabling
developers to use FPGA's potential without extensive hardware knowledge. Hence, this
thesis focuses on accelerating the computationally intensive part of the most apparent
distortion (MAD) algorithm on FPGA using OpenCL. The results are compared with CPU
implementation to evaluate performance and efficiency gains.
ContributorsGunavelu Mohan, Aswin (Author) / Sohoni, Sohum (Thesis advisor) / Ren, Fengbo (Thesis advisor) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2017