Matching Items (26)
Filtering by
- All Subjects: Electrical Engineering
- Genre: Doctoral Dissertation
- Creators: Goodnick, Stephen
Description
One of the challenges in future semiconductor device design is excessive rise of power dissipation and device temperatures. With the introduction of new geometrically confined device structures like SOI, FinFET, nanowires and continuous incorporation of new materials with poor thermal conductivities in the device active region, the device thermal problem is expected to become more challenging in coming years. This work examines the degradation in the ON-current due to self-heating effects in 10 nm channel length silicon nanowire transistors. As part of this dissertation, a 3D electrothermal device simulator is developed that self-consistently solves electron Boltzmann transport equation with 3D energy balance equations for both the acoustic and the optical phonons. This device simulator predicts temperature variations and other physical and electrical parameters across the device for different bias and boundary conditions. The simulation results show insignificant current degradation for nanowire self-heating because of pronounced velocity overshoot effect. In addition, this work explores the role of various placement of the source and drain contacts on the magnitude of self-heating effect in nanowire transistors. This work also investigates the simultaneous influence of self-heating and random charge effects on the magnitude of the ON current for both positively and negatively charged single charges. This research suggests that the self-heating effects affect the ON-current in two ways: (1) by lowering the barrier at the source end of the channel, thus allowing more carriers to go through, and (2) via the screening effect of the Coulomb potential. To examine the effect of temperature dependent thermal conductivity of thin silicon films in nanowire transistors, Selberherr's thermal conductivity model is used in the device simulator. The simulations results show larger current degradation because of self-heating due to decreased thermal conductivity . Crystallographic direction dependent thermal conductivity is also included in the device simulations. Larger degradation is observed in the current along the [100] direction when compared to the [110] direction which is in agreement with the values for the thermal conductivity tensor provided by Zlatan Aksamija.
ContributorsHossain, Arif (Author) / Vasileska, Dragica (Thesis advisor) / Ahmed, Shaikh (Committee member) / Bakkaloglu, Bertan (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2011
Description
In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work, the integration of random defects positioned across the channel at the Si:SiO2 interface from source end to the drain end in the presence of different random dopant distributions are used to conduct Ensemble Monte-Carlo ( EMC ) based numerical simulation of key device performance metrics for 45 nm gate length MOSFET device. The two main performance parameters that affect RTS based reliability measurements are percentage change in threshold voltage and percentage change in drain current fluctuation in the saturation region. It has been observed as a result of the simulation that changes in both and values moderately decrease as the defect position is gradually moved from source end to the drain end of the channel. Precise analytical device physics based model needs to be developed to explain and assess the EMC simulation based higher VT fluctuations as experienced for trap positions at the source side. A new analytical model has been developed that simultaneously takes account of dopant number variations in the channel and depletion region underneath and carrier mobility fluctuations resulting from fluctuations in surface potential barriers. Comparisons of this new analytical model along with existing analytical models are shown to correlate with 3D EMC simulation based model for assessment of VT fluctuations percentage induced by a single interface trap. With scaling of devices beyond 32 nm node, halo doping at the source and drain are routinely incorporated to combat the threshold voltage roll-off that takes place with effective channel length reduction. As a final study on this regard, 3D EMC simulation method based computations of threshold voltage fluctuations have been performed for varying source and drain halo pocket length to illustrate the threshold voltage fluctuations related reliability problems that have been aggravated by trap positions near the source at the interface compared to conventional 45 nm MOSFET.
ContributorsAshraf, Nabil Shovon (Author) / Vasileska, Dragica (Thesis advisor) / Schroder, Dieter (Committee member) / Goodnick, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Description
As existing solar cell technologies come closer to their theoretical efficiency, new concepts that overcome the Shockley-Queisser limit and exceed 50% efficiency need to be explored. New materials systems are often investigated to achieve this, but the use of existing solar cell materials in advanced concept approaches is compelling for multiple theoretical and practical reasons. In order to include advanced concept approaches into existing materials, nanostructures are used as they alter the physical properties of these materials. To explore advanced nanostructured concepts with existing materials such as III-V alloys, silicon and/or silicon/germanium and associated alloys, fundamental aspects of using these materials in advanced concept nanostructured solar cells must be understood. Chief among these is the determination and predication of optimum electronic band structures, including effects such as strain on the band structure, and the material's opto-electronic properties. Nanostructures have a large impact on band structure and electronic properties through quantum confinement. An additional large effect is the change in band structure due to elastic strain caused by lattice mismatch between the barrier and nanostructured (usually self-assembled QDs) materials. To develop a material model for advanced concept solar cells, the band structure is calculated for single as well as vertical array of quantum dots with the realistic effects such as strain, associated with the epitaxial growth of these materials. The results show significant effect of strain in band structure. More importantly, the band diagram of a vertical array of QDs with different spacer layer thickness show significant change in band offsets, especially for heavy and light hole valence bands when the spacer layer thickness is reduced. These results, ultimately, have significance to develop a material model for advance concept solar cells that use the QD nanostructures as absorbing medium. The band structure calculations serve as the basis for multiple other calculations. Chief among these is that the model allows the design of a practical QD advanced concept solar cell, which meets key design criteria such as a negligible valence band offset between the QD/barrier materials and close to optimum band gaps, resulting in the predication of optimum material combinations.
ContributorsDahal, Som Nath (Author) / Honsberg, Christiana (Thesis advisor) / Goodnick, Stephen (Committee member) / Roedel, Ronald (Committee member) / Ponce, Fernando (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT An Ensemble Monte Carlo (EMC) computer code has been developed to simulate, semi-classically, spin-dependent electron transport in quasi two-dimensional (2D) III-V semiconductors. The code accounts for both three-dimensional (3D) and quasi-2D transport, utilizing either 3D or 2D scattering mechanisms, as appropriate. Phonon, alloy, interface roughness, and impurity scattering mechanisms are included, accounting for the Pauli Exclusion Principle via a rejection algorithm. The 2D carrier states are calculated via a self-consistent 1D Schrödinger-3D-Poisson solution in which the charge distribution of the 2D carriers in the quantization direction is taken as the spatial distribution of the squared envelope functions within the Hartree approximation. The wavefunctions, subband energies, and 2D scattering rates are updated periodically by solving a series of 1D Schrödinger wave equations (SWE) over the real-space domain of the device at fixed time intervals. The electrostatic potential is updated by periodically solving the 3D Poisson equation. Spin-polarized transport is modeled via a spin density-matrix formalism that accounts for D'yakanov-Perel (DP) scattering. Also, the code allows for the easy inclusion of additional scattering mechanisms and structural modifications to devices. As an application of the simulator, the current voltage characteristics of an InGaAs/InAlAs HEMT are simulated, corresponding to nanoscale III-V HEMTs currently being fabricated by Intel Corporation. The comparative effects of various scattering parameters, material properties and structural attributes are investigated and compared with experiments where reasonable agreement is obtained. The spatial evolution of spin-polarized carriers in prototypical Spin Field Effect Transistor (SpinFET) devices is then simulated. Studies of the spin coherence times in quasi-2D structures is first investigated and compared to experimental results. It is found that the simulated spin coherence times for GaAs structures are in reasonable agreement with experiment. The SpinFET structure studied is a scaled-down version of the InGaAs/InAlAs HEMT discussed in this work, in which spin-polarized carriers are injected at the source, and the coherence length is studied as a function of gate voltage via the Rashba effect.
ContributorsTierney, Brian David (Author) / Goodnick, Stephen (Thesis advisor) / Ferry, David (Committee member) / Akis, Richard (Committee member) / Saraniti, Marco (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
Description
The research of alternative materials and new device architectures to exceed the limits of conventional silicon-based devices has been sparked by the persistent pursuit of semiconductor technology scaling. The development of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2), well-known member of the transition metal dichalcogenide (TMD) family, has made great strides towards ultrascaled two-dimensional (2D) field-effect-transistors (FETs). The scaling issues facing silicon-based complementary metal-oxide-semiconductor (CMOS) technologies can be solved by 2D FETs, which show extraordinary potential.This dissertation provides a comprehensive experimental analysis relating to improvements in p-type metal-oxide-semiconductor (PMOS) FETs with few-layer WSe2 and high-κ metal gate (HKMG) stacks. Compared to this works improved methods, standard metallization (more damaging to underlying channel) results in significant Fermi-level pinning, although Schottky barrier heights remain small (< 100 meV) when using high work function metals. Temperature-dependent analysis reveals a dominant contribution to contact resistance from the damaged channel access region. Thus, through less damaging metallization methods combined with strongly scaled HKMG stacks significant improvements were achieved in contact resistance and PMOS FET overall performance. A clean contact/channel interface was achieved through high-vacuum evaporation and temperature-controlled stepped deposition. Theoretical analysis using a Landauer transport adapted to WSe2 Schottky barrier FETs (SB-FETs) elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance towards the ultimate CMOS scaling limit.
Next, this dissertation discusses how device electrical characteristics are affected by scaling of equivalent oxide thickness (EOT) and by adopting double-gate FET architectures, as well as how this might support CMOS scaling. An improved gate control over the channel is made possible by scaling EOT, improving on-off current ratios, carrier mobility, and subthreshold swing. This study also elucidates the impact of EOT scaling on FET gate hysteresis attributed to charge-trapping effects in high-κ-dielectrics prepared by atomic layer deposition (ALD). These developments in 2D FETs offer a compelling alternative to conventional silicon-based devices and a path for continued transistor scaling. This research contributes to ongoing efforts in 2D materials for future semiconductor technologies. Finally, this work introduces devices based on emerging Janus TMDs and bismuth oxyselenide (Bi2O2Se) layered semiconductors.
ContributorsPatoary, Md Naim Hossain (Author) / Sanchez Esqueda, Ivan (Thesis advisor) / Tongay, Sefaattin (Committee member) / Vasileska, Dragica (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2023
Description
Gallium Nitride (GaN) is uniquely suited for Radio Frequency (RF) and power electronic applications due to its intrinsically high saturation velocity and high mobility compared to Silicon and Silicon Carbide (SiC). High Electron Mobility Transistors (HEMTs) have remained the primary topology for GaN transistors in RF applications. However, GaN HEMTs suffer from a variety of issues such as current crowding, lack of enhancement mode (E-Mode) operation and non-linearity. These drawbacks slow the widespread adoption of GaN devices for ultra-low voltage (ULV) applications such as voltage regulators, automotive and computing applications. E-mode operation is especially desired in low-voltage high frequency switching applications. In this context, Fin Field Effect Transistors (FinFETs) offer an alternative topology for ULV applications as opposed to conventional HEMTs. Recent advances in material processing, high aspect ratio epitaxial growth and etching methods has led to an increased interest in 3D nanostructures such as Nano-FinFETs and Nanowire FETs. A typical 3D nano-FinFET is the AlGaN/GaN Metal Insulator Semiconductor (MIS) FET wherein a layer of Al2O3 surrounds the AlGaN/GaN fin. The presence of the side gates leads to additional lateral confinement of the 2D Electron Gas (2DEG). Theoretical calculations of transport properties in confined systems such as AlGaN/GaN Finfets are scarce compared to those of their planar HEMT counterparts.
A novel simulator is presented in this dissertation, which employs self-consistent solution of the coupled 1D Boltzmann – 2D Schrödinger – 3D Poisson problem, to yield the channel electrostatics and the low electric field transport characteristics of AlGaN/GaN MIS FinFETs. The low field electron mobility is determined by solving the Boltzmann transport equation in the Quasi-1D region using 1D Ensemble Monte Carlo method. Three electron-phonon scattering mechanisms (acoustic, piezoelectric and polar optical phonon scattering) and interface roughness scattering at the AlGaN/GaN interface are considered in this theoretical model. Simulated low-field electron mobility and its temperature dependence are in agreement with experimental data reported in the literature.
A quasi-1D version of alloy clustering model is derived and implemented and the limiting effect of alloy clustering on the low-field electron mobility is investigated for the first time for MIS FinFET device structures.
ContributorsKumar, Viswanathan Naveen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Nemanich, Robert (Committee member) / Povolotskyi, Michael (Committee member) / Esqueda, Ivan Sanchez (Committee member) / Arizona State University (Publisher)
Created2022
Description
The advent of silicon, germanium, narrow-gap III-V materials, and later the wide bandgap (WBG) semiconductors, and their subsequent revolution and enrichment of daily life begs the question: what is the next generation of semiconductor electronics poised to look like? Ultrawide bandgap (UWBG) semiconductors are the class of semiconducting materials that possess an electronic bandgap (EG) greater than that of gallium nitride (GaN), which is 3.4 eV. They currently consist of beta-phase gallium oxide (β-Ga2O3 ; EG = 4.6–4.9 eV), diamond (EG = 5.5 eV), aluminum nitride (AlN; EG =6.2 eV), cubic boron nitride (BN; EG = 6.4 eV), and other materials hitherto undiscovered. Such a strong emphasis is placed on the semiconductor bandgap because so many relevant electronic performance properties scale positively with the bandgap. Where power electronics is concerned, the Baliga's Figure of Merit (BFOM) quantifies how much voltage a device can block in the off state and how high its conductivity is in the on state. The BFOM has a sixth-order dependence on the bandgap. The UWBG class of semiconductors also possess the potential for higher switching efficiencies and power densities and better suitability for deep-UV and RF optoelectronics. Many UWBG materials have very tight atomic lattices and high displacement energies, which makes them suitable for extreme applications such as radiation-harsh environments commonly found in military, industrial, and outer space applications. In addition, the UWBG materials also show promise for applications in quantum information sciences. For all the inherent promise and burgeoning research efforts, key breakthroughs in UWBG research have only occurred as recently as within the last two to three decades, making them extremely immature in comparison with the well-known WBG materials and others before them. In particular, AlN suffers from a lack of wide availability of low-cost, highquality substrates, a stark contrast to β-Ga2O3, which is now readily commercially available. In order to realize more efficient and varied devices on the relatively nascent UWBG materials platform, a deeper understanding of the various devices and physics is necessary. The following thesis focuses on the UWBG materials AlN and β-Ga2O3, overlooking radiation studies, a novel device heterojunction, and electronic defect study.
ContributorsMontes, Jossue (Author) / Zhao, Yuji (Thesis advisor) / Vasileska, Dragica (Committee member) / Goodnick, Stephen (Committee member) / Sanchez Esqueda, Ivan (Committee member) / Arizona State University (Publisher)
Created2021
Description
As the single-junction silicon solar cell is approaching its theoretical efficiency limits, the loss from shading and resistance is gaining increasing attention. The metal grid pattern may cause an efficiency loss up to 1–3%abs (absolute percentage) depending on the grid’s materials and structure.Many attempts have been proposed to reduce the loss caused by the contacts and module. Among them, the monolithic solar cell, which is a solar cell with multiple string cells on the same wafer and connected in a series, presents advantages of low output current, busbar-free contact, minimized interconnection space, and ohmic loss reduction. However, this structure also introduces a lateral forward bias current through the base region, which severely degrades the cell’s performance. In addition, this interconnection in the base region has partially shunted certain solar cells in the monolithic cell, which created a mismatch between string cells.
For the last few decades, researchers have used different methods such as etching trenches or enlarging the distance between the neighboring string cells to solve this problem. However, these methods were both ineffective and defective.
In this work, a novel method of suppressing the lateral forward bias current is proposed. By adding a very high surface recombination to the mid-region between the string cells, the carrier density in the mid-region can be decreased close to the doping density. Thus, the resistivity in the mid-region can be increased tenfold or more. As a result, the lateral forward bias current is greatly reduced.
Other methods to reduce lateral forward bias current include optimizing the width of the mid-region, shading the mid-region, reducing the base doping and base thickness which can be used to reduce the mismatch as well.
Another method has been proposed to calculate the minimum efficiency loss of a monolithic cell compared to the baseline solar cell. As a result, the monolithic cell could potentially gain more advantages over the baseline solar cells with a thinner and low-doped wafer.
A monolithic solar cell with innovative designs is presented in this work which shows an efficiency that is potentially higher than that of normal solar cells.
ContributorsXue, Shujian (Author) / Bowden, Studart (Thesis advisor) / Goodnick, Stephen (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2022
Description
Wide Bandgap (WBG) semiconductor materials are shaping day-to-day technologyby introducing powerful and more energy responsible devices. These materials have
opened the door for building basic semiconductor devices which are superior in terms of
handling high voltages, high currents, power, and temperature which is not possible using
conventional silicon technology. As the research continues in the field of WBG based
devices, there is a potential chance that the power electronics industry can save billions of
dollars deploying energy-efficient circuits in high power conversion electronics. Diamond,
silicon carbide and gallium nitride are the top three contenders among which diamond can
significantly outmatch others in a variety of properties. However, diamond technology is
still in its early phase of development and there are challenges involved in many aspects of
processing a successful integrated circuit. The work done in this research addresses three
major aspects of problems related to diamond technology. In the first part, the applicability
of compact modeling and Technology Computer-Aided Design (TCAD) modeling
technique for diamond Schottky p-i-n diodes has been demonstrated. The compact model
accurately predicts AC, DC and nonlinear behavior of the diode required for fast circuit
simulation. Secondly, achieving low resistance ohmic contact onto n-type diamond is one
of the major issues that is still an open research problem as it determines the performance
of high-power RF circuits and switching losses in power converters circuits. So, another
portion of this thesis demonstrates the achievement of very low resistance ohmic contact
(~ 10-4 Ω⋅cm2) onto n-type diamond using nano crystalline carbon interface layer. Using
the developed TCAD and compact models for low resistance contacts, circuit level
predictions show improvements in RF performance. Lastly, an initial study of breakdown
characteristics of diamond and cubic boron nitride heterostructure is presented. This study
serves as a first step for making future transistors using diamond and cubic boron nitride –
a very less explored material system in literature yet promising for extreme circuit
applications involving high power and temperature.
ContributorsJHA, VISHAL (Author) / Thornton, Trevor (Thesis advisor) / Goodnick, Stephen (Committee member) / Nemanich, Robert (Committee member) / Alford, Terry (Committee member) / Hoque, Mazhar (Committee member) / Arizona State University (Publisher)
Created2023
Description
An efficient thermal solver is available in the CMC that allows modeling self-heating in the electrical simulations, which treats phonons as flux and solves the energy balance equation to quantify thermal effects. Using this solver, thermal simulations were performed on GaN-HEMTs in order to test effect of gate architectures on the DC and RF performance of the device. A Π- gate geometry is found to suppress 19.75% more hot electrons corresponding to a DC power of 2.493 W/mm for Vgs = -0.6V (max transconductance) with respect to the initial T-gate. For the DC performance, the output current, Ids is nearly same for each device configuration over the entire bias range. For the RF performance, the current gain was evaluated over a frequency range 20 GHz to 120 GHz in each device for both thermal (including self-heating) and isothermal (without self-heating). The evaluated cutoff frequency is around 7% lower for the thermal case than the isothermal case. The simulated cutoff frequency closely follows the experimental cutoff frequency. The work was extended to the study of ultra-wide bandgap material (Diamond), where isotope effect causes major deterioration in thermal conductivity. In this case, bulk phonons are modeled as semiclassical particles solving the nonlinear Peierls - Boltzmann transport equation with a stochastic approach. Simulations were performed for 0.001% (ultra-pure), 0.1% and 1.07% isotope concentration (13C) of diamond, showing good agreement with the experimental values. Further investigation was performed on the effect of isotope on the dynamics of individual phonon branches, thermal conductivity and the mean free path, to identify the dominant phonon branch. Acoustic phonons are found to be the principal contributors to thermal conductivity across all isotope concentrations with transverse acoustic (TA2) branch is the dominant branch with a contribution of 40% at room temperature and 37% at 500K. Mean free path computations show the lower bound of device dimensions in order to obtain maximum thermal conductivity. At 300K, the lowest mean free path (which is attributed to Longitudinal Optical phonon) reduces from 24nm to 8 nm for isotope concentration of 0.001% and 1.07% respectively. Similarly, the maximum mean free path (which is attributed to Longitudinal Acoustic phonon) reduces from 4 µm to 3.1 µm, respectively, for the same isotope concentrations. Furthermore, PETSc (Portable, Extensible Toolkit for Scientific Computation) developed by Argonne National Lab, was included in the existing Cellular Monte Carlo device simulator as a Poisson solver to further extend the capability of the simulator. The validity of the solver was tested performing 2D and 3D simulations and the results were compared with the well-established multigrid Poisson solver.
ContributorsAcharjee, Joy (Author) / Saraniti, Marco (Thesis advisor) / Goodnick, Stephen (Committee member) / Thornton, Trevor (Committee member) / Wang, Robert (Committee member) / Arizona State University (Publisher)
Created2024