Matching Items (51)
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- All Subjects: Electrical Engineering
- Genre: Masters Thesis
- Creators: Barnaby, Hugh
- Creators: Vasileska, Dragica
- Member of: ASU Electronic Theses and Dissertations
Description
Solar energy, including solar heating, solar architecture, solar thermal electricity and solar photovoltaics, is one of the primary energy sources replacing fossil fuels. Being one of the most important techniques, significant research has been conducted in solar cell efficiency improvement. Simulation of various structures and materials of solar cells provides a deeper understanding of device operation and ways to improve their efficiency. Over the last two decades, polycrystalline thin-film Cadmium-Sulfide and Cadmium-Telluride (CdS/CdTe) solar cells fabricated on glass substrates have been considered as one of the most promising candidate in the photovoltaic technologies, for their similar efficiency and low costs when compared to traditional silicon-based solar cells. In this work a fast one dimensional time-dependent/steady-state drift-diffusion simulator, accelerated by adaptive non-uniform mesh and automatic time-step control, for modeling solar cells has been developed and has been used to simulate a CdS/CdTe solar cell. These models are used to reproduce transients of carrier transport in response to step-function signals of different bias and varied light intensity. The time-step control models are also used to help convergence in steady-state simulations where constrained material constants, such as carrier lifetimes in the order of nanosecond and carrier mobility in the order of 100 cm2/Vs, must be applied.
ContributorsGuo, Da (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen M (Committee member) / Sankin, Igor (Committee member) / Arizona State University (Publisher)
Created2013
Description
ABSTRACT Developing new non-traditional device models is gaining popularity as the silicon-based electrical device approaches its limitation when it scales down. Membrane systems, also called P systems, are a new class of biological computation model inspired by the way cells process chemical signals. Spiking Neural P systems (SNP systems), a certain kind of membrane systems, is inspired by the way the neurons in brain interact using electrical spikes. Compared to the traditional Boolean logic, SNP systems not only perform similar functions but also provide a more promising solution for reliable computation. Two basic neuron types, Low Pass (LP) neurons and High Pass (HP) neurons, are introduced. These two basic types of neurons are capable to build an arbitrary SNP neuron. This leads to the conclusion that these two basic neuron types are Turing complete since SNP systems has been proved Turing complete. These two basic types of neurons are further used as the elements to construct general-purpose arithmetic circuits, such as adder, subtractor and comparator. In this thesis, erroneous behaviors of neurons are discussed. Transmission error (spike loss) is proved to be equivalent to threshold error, which makes threshold error discussion more universal. To improve the reliability, a new structure called motif is proposed. Compared to Triple Modular Redundancy improvement, motif design presents its efficiency and effectiveness in both single neuron and arithmetic circuit analysis. DRAM-based CMOS circuits are used to implement the two basic types of neurons. Functionality of basic type neurons is proved using the SPICE simulations. The motif improved adder and the comparator, as compared to conventional Boolean logic design, are much more reliable with lower leakage, and smaller silicon area. This leads to the conclusion that SNP system could provide a more promising solution for reliable computation than the conventional Boolean logic.
ContributorsAn, Pei (Author) / Cao, Yu (Thesis advisor) / Barnaby, Hugh (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2013
Description
GaN high electron mobility transistors (HEMTs) based on the III-V nitride material system have been under extensive investigation because of their superb performance as high power RF devices. Two dimensional electron gas(2-DEG) with charge density ten times higher than that of GaAs-based HEMT and mobility much higher than Si enables a low on-resistance required for RF devices. Self-heating issues with GaN HEMT and lack of understanding of various phenomena are hindering their widespread commercial development. There is a need to understand device operation by developing a model which could be used to optimize electrical and thermal characteristics of GaN HEMT design for high power and high frequency operation. In this thesis work a physical simulation model of AlGaN/GaN HEMT is developed using commercially available software ATLAS from SILVACO Int. based on the energy balance/hydrodynamic carrier transport equations. The model is calibrated against experimental data. Transfer and output characteristics are the key focus in the analysis along with saturation drain current. The resultant IV curves showed a close correspondence with experimental results. Various combinations of electron mobility, velocity saturation, momentum and energy relaxation times and gate work functions were attempted to improve IV curve correlation. Thermal effects were also investigated to get a better understanding on the role of self-heating effects on the electrical characteristics of GaN HEMTs. The temperature profiles across the device were observed. Hot spots were found along the channel in the gate-drain spacing. These preliminary results indicate that the thermal effects do have an impact on the electrical device characteristics at large biases even though the amount of self-heating is underestimated with respect to thermal particle-based simulations that solve the energy balance equations for acoustic and optical phonons as well (thus take proper account of the formation of the hot-spot). The decrease in drain current is due to decrease in saturation carrier velocity. The necessity of including hydrodynamic/energy balance transport models for accurate simulations is demonstrated. Possible ways for improving model accuracy are discussed in conjunction with future research.
ContributorsChowdhury, Towhid (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Since its inception about three decades ago, silicon on insulator (SOI) technology has come a long way to be included in the microelectronics roadmap. Earlier, scientists and engineers focused on ways to increase the microprocessor clock frequency and speed. Today, with smart phones and tablets gaining popularity, power consumption has become a major factor. In this thesis, self-heating effects in a 25nm fully depleted (FD) SOI device are studied by implementing a 2-D particle based device simulator coupled self-consistently with the energy balance equations for both acoustic and optical phonons. Semi-analytical expressions for acoustic and optical phonon scattering rates (all modes) are derived and evaluated using quadratic dispersion relationships. Moreover, probability distribution functions for the final polar angle after scattering is also computed and the rejection technique is implemented for its selection. Since the temperature profile varies throughout the device, temperature dependent scattering tables are used for the electron transport kernel. The phonon energy balance equations are also modified to account for inelasticity in acoustic phonon scattering for all branches. Results obtained from this simulation help in understanding self-heating and the effects it has on the device characteristics. The temperature profiles in the device show a decreasing trend which can be attributed to the inelastic interaction between the electrons and the acoustic phonons. This is further proven by comparing the temperature plots with the simulation results that assume the elastic and equipartition approximation for acoustic and the Einstein model for optical phonons. Thus, acoustic phonon inelasticity and the quadratic phonon dispersion relationships play a crucial role in studying self-heating effects.
ContributorsGada, Manan Laxmichand (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David K. (Committee member) / Goodnick, Stephen M (Committee member) / Arizona State University (Publisher)
Created2013
Description
The dissolution of metal layers such as silver into chalcogenide glass layers such as germanium selenide changes the resistivity of the metal and chalcogenide films by a great extent. It is known that the incorporation of the metal can be achieved by ultra violet light exposure or thermal processes. In this work, the use of metal dissolution by exposure to gamma radiation has been explored for radiation sensor applications. Test structures were designed and a process flow was developed for prototype sensor fabrication. The test structures were designed such that sensitivity to radiation could be studied. The focus is on the effect of gamma rays as well as ultra violet light on silver dissolution in germanium selenide (Ge30Se70) chalcogenide glass. Ultra violet radiation testing was used prior to gamma exposure to assess the basic mechanism. The test structures were electrically characterized prior to and post irradiation to assess resistance change due to metal dissolution. A change in resistance was observed post irradiation and was found to be dependent on the radiation dose. The structures were also characterized using atomic force microscopy and roughness measurements were made prior to and post irradiation. A change in roughness of the silver films on Ge30Se70 was observed following exposure. This indicated the loss of continuity of the film which causes the increase in silver film resistance following irradiation. Recovery of initial resistance in the structures was also observed after the radiation stress was removed. This recovery was explained with photo-stimulated deposition of silver from the chalcogenide at room temperature confirmed with the re-appearance of silver dendrites on the chalcogenide surface. The results demonstrate that it is possible to use the metal dissolution effect in radiation sensing applications.
ContributorsChandran, Ankitha (Author) / Kozicki, Michael N (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
ABSTRACT This work seeks to develop a practical solution for short range ultrasonic communications and produce an integrated array of acoustic transmitters on a flexible substrate. This is done using flexible thin film transistor (TFT) and micro electromechanical systems (MEMS). The goal is to develop a flexible system capable of communicating in the ultrasonic frequency range at a distance of 10 - 100 meters. This requires a great deal of innovation on the part of the FDC team developing the TFT driving circuitry and the MEMS team adapting the technology for fabrication on a flexible substrate. The technologies required for this research are independently developed. The TFT development is driven primarily by research into flexible displays. The MEMS development is driving by research in biosensors and micro actuators. This project involves the integration of TFT flexible circuit capabilities with MEMS micro actuators in the novel area of flexible acoustic transmitter arrays. This thesis focuses on the design, testing and analysis of the circuit components required for this project.
ContributorsDaugherty, Robin (Author) / Allee, David R. (Thesis advisor) / Chae, Junseok (Thesis advisor) / Aberle, James T (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2012
Description
The goal of this research work is to develop a particle-based device simulator for modeling strained silicon devices. Two separate modules had to be developed for that purpose: A generic bulk Monte Carlo simulation code which in the long-time limit solves the Boltzmann transport equation for electrons; and an extension to this code that solves for the bulk properties of strained silicon. One scattering table is needed for conventional silicon, whereas, because of the strain breaking the symmetry of the system, three scattering tables are needed for modeling strained silicon material. Simulation results for the average drift velocity and the average electron energy are in close agreement with published data. A Monte Carlo device simulation tool has also been employed to integrate the effects of self-heating into device simulation for Silicon on Insulator devices. The effects of different types of materials for buried oxide layers have been studied. Sapphire, Aluminum Nitride (AlN), Silicon dioxide (SiO2) and Diamond have been used as target materials of interest in the analysis and the effects of varying insulator layer thickness have also been investigated. It was observed that although AlN exhibits the best isothermal behavior, diamond is the best choice when thermal effects are accounted for.
ContributorsQazi, Suleman (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Tao, Meng (Committee member) / Arizona State University (Publisher)
Created2013
Description
The advent of threshold logic simplifies the traditional Boolean logic to the single level multi-input function. Threshold logic latch (TLL), among implementations of threshold logic, is functionally equivalent to a multi-input function with an edge triggered flip-flop, which stands out to improve area and both dynamic and leakage power consumption, providing an appropriate design alternative. Accordingly, the TLL standard cell library is designed. Through technology mapping, hybrid circuit is generated by absorbing the logic cone backward from each flip-flip to get the smallest remaining feeder. With the scan test methodology adopted, design for testability (DFT) is proposed, including scan element design and scan chain insertion. Test synthesis flow is then introduced, according to the Cadence tool, RTL compiler. Test application is the process of applying vectors and the response analysis, which is mainly about the testbench design. A parameterized generic self-checking Verilog testbench is designed for static fault detection. Test development refers to the fault modeling, and test generation. Firstly, functional truth table test generation on TLL cells is proposed. Before the truth table test of the threshold function, the dependence of sequence of vectors applied, i.e., the dependence of current state on the previous state, should be eliminated. Transition test (dynamic pattern) on all weak inputs is proved to be able to test the reset function, which is supposed to erase the history in the reset phase before every evaluation phase. Remaining vectors in the truth table except the weak inputs are then applied statically (static pattern). Secondly, dynamic patterns for all weak inputs are proposed to detect structural transistor level faults analyzed in the TLL cell, with single fault assumption and stuck-at faults, stuck-on faults, and stuck-open faults under consideration. Containing those patterns, the functional test covers all testable structural faults inside the TLL. Thirdly, with the scope of the whole hybrid netlist, the procedure of test generation is proposed with three steps: scan chain test; test of feeders and other scan elements except TLLs; functional pattern test of TLL cells. Implementation of this procedure is discussed in the automatic test pattern generation (ATPG) chapter.
ContributorsHu, Yang (Author) / Vrudhula, Sarma (Thesis advisor) / Barnaby, Hugh (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2013
Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
There is an ever growing need for larger memories which are reliable and fast. New technologies to implement non-volatile memories which are large, fast, compact and cost-efficient are being studied extensively. One of the most promising technologies being developed is the resistive RAM (ReRAM). In ReRAM the resistance of the device varies with the voltage applied across it. Programmable metallization cells (PMC) is one of the devices belonging to this category of non-volatile memories.
In order to advance the development of these devices, there is a need to develop simulation models which replicate the behavior of these devices in circuits. In this thesis, a verilogA model for the PMC has been developed. The behavior of the model has been tested using DC and transient simulations. Experimental data obtained from testing PMC devices fabricated at Arizona State University have been compared to results obtained from simulation.
A basic memory cell known as the 1T 1R cell built using the PMC has also been simulated and verified. These memory cells have the potential to be building blocks of large scale memories. I believe that the verilogA model developed in this thesis will prove to be a powerful tool for researchers and circuit developers looking to develop non-volatile memories using alternative technologies.
In order to advance the development of these devices, there is a need to develop simulation models which replicate the behavior of these devices in circuits. In this thesis, a verilogA model for the PMC has been developed. The behavior of the model has been tested using DC and transient simulations. Experimental data obtained from testing PMC devices fabricated at Arizona State University have been compared to results obtained from simulation.
A basic memory cell known as the 1T 1R cell built using the PMC has also been simulated and verified. These memory cells have the potential to be building blocks of large scale memories. I believe that the verilogA model developed in this thesis will prove to be a powerful tool for researchers and circuit developers looking to develop non-volatile memories using alternative technologies.
ContributorsBharadwaj, Vineeth (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Mikkola, Esko (Committee member) / Arizona State University (Publisher)
Created2014