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Description
Flow measurement has always been one of the most critical processes in many industrial and clinical applications. The dynamic behavior of flow helps to define the state of a process. An industrial example would be that in an aircraft, where the rate of airflow passing the aircraft is used to

Flow measurement has always been one of the most critical processes in many industrial and clinical applications. The dynamic behavior of flow helps to define the state of a process. An industrial example would be that in an aircraft, where the rate of airflow passing the aircraft is used to determine the speed of the plane. A clinical example would be that the flow of a patient's breath which could help determine the state of the patient's lungs. This project is focused on the flow-meter that are used for airflow measurement in human lungs. In order to do these measurements, resistive-type flow-meters are commonly used in respiratory measurement systems. This method consists of passing the respiratory flow through a fluid resistive component, while measuring the resulting pressure drop, which is linearly related to volumetric flow rate. These types of flow-meters typically have a low frequency response but are adequate for most applications, including spirometry and respiration monitoring. In the case of lung parameter estimation methods, such as the Quick Obstruction Method, it becomes important to have a higher frequency response in the flow-meter so that the high frequency components in the flow are measurable. The following three types of flow-meters were: a. Capillary type b. Screen Pneumotach type c. Square Edge orifice type To measure the frequency response, a sinusoidal flow is generated with a small speaker and passed through the flow-meter that is connected to a large, rigid container. True flow is proportional to the derivative of the pressure inside the container. True flow is then compared with the measured flow, which is proportional to the pressure drop across the flow-meter. In order to do the characterization, two LabVIEW data acquisition programs have been developed, one for transducer calibration, and another one that records flow and pressure data for frequency response testing of the flow-meter. In addition, a model that explains the behavior exhibited by the flow-meter has been proposed and simulated. This model contains a fluid resistor and inductor in series. The final step in this project was to approximate the frequency response data to the developed model expressed as a transfer function.
ContributorsHu, Jianchen (Author) / Macia, Narciso (Thesis advisor) / Pollat, Scott (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Photovoltaic (PV) module nameplates typically provide the module's electrical characteristics at standard test conditions (STC). The STC conditions are: irradiance of 1000 W/m2, cell temperature of 25oC and sunlight spectrum at air mass 1.5. However, modules in the field experience a wide range of environmental conditions which affect their electrical

Photovoltaic (PV) module nameplates typically provide the module's electrical characteristics at standard test conditions (STC). The STC conditions are: irradiance of 1000 W/m2, cell temperature of 25oC and sunlight spectrum at air mass 1.5. However, modules in the field experience a wide range of environmental conditions which affect their electrical characteristics and render the nameplate data insufficient in determining a module's overall, actual field performance. To make sound technical and financial decisions, designers and investors need additional performance data to determine the energy produced by modules operating under various field conditions. The angle of incidence (AOI) of sunlight on PV modules is one of the major parameters which dictate the amount of light reaching the solar cells. The experiment was carried out at the Arizona State University- Photovoltaic Reliability Laboratory (ASU-PRL). The data obtained was processed in accordance with the IEC 61853-2 model to obtain relative optical response of the modules (response which does not include the cosine effect). The results were then compared with theoretical models for air-glass interface and also with the empirical model developed by Sandia National Laboratories. The results showed that all modules with glass as the superstrate had identical optical response and were in agreement with both the IEC 61853-2 model and other theoretical and empirical models. The performance degradation of module over years of exposure in the field is dependent upon factors such as environmental conditions, system configuration, etc. Analyzing the degradation of power and other related performance parameters over time will provide vital information regarding possible degradation rates and mechanisms of the modules. An extensive study was conducted by previous ASU-PRL students on approximately 1700 modules which have over 13 years of hot- dry climatic field condition. An analysis of the results obtained in previous ASU-PRL studies show that the major degradation in crystalline silicon modules having glass/polymer construction is encapsulant discoloration (causing short circuit current drop) and solder bond degradation (causing fill factor drop due to series resistance increase). The power degradation for crystalline silicon modules having glass/glass construction was primarily attributed to encapsulant delamination (causing open-circuit voltage drop).
ContributorsVasantha Janakeeraman, Suryanarayana (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Macia, Narciso (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Radio frequency (RF) transceivers require a disproportionately high effort in terms of test development time, test equipment cost, and test time. The relatively high test cost stems from two contributing factors. First, RF transceivers require the measurement of a diverse set of specifications, requiring multiple test set-ups and long test

Radio frequency (RF) transceivers require a disproportionately high effort in terms of test development time, test equipment cost, and test time. The relatively high test cost stems from two contributing factors. First, RF transceivers require the measurement of a diverse set of specifications, requiring multiple test set-ups and long test times, which complicates load-board design, debug, and diagnosis. Second, high frequency operation necessitates the use of expensive equipment, resulting in higher per second test time cost compared with mixed-signal or digital circuits. Moreover, in terms of the non-recurring engineering cost, the need to measure complex specfications complicates the test development process and necessitates a long learning process for test engineers. Test time is dominated by changing and settling time for each test set-up. Thus, single set-up test solutions are desirable. Loop-back configuration where the transmitter output is connected to the receiver input are used as the desirable test set- up for RF transceivers, since it eliminates the reliance on expensive instrumentation for RF signal analysis and enables measuring multiple parameters at once. In-phase and Quadrature (IQ) imbalance, non-linearity, DC offset and IQ time skews are some of the most detrimental imperfections in transceiver performance. Measurement of these parameters in the loop-back mode is challenging due to the coupling between the receiver (RX) and transmitter (TX) parameters. Loop-back based solutions are proposed in this work to resolve this issue. A calibration algorithm for a subset of the above mentioned impairments is also presented. Error Vector Magnitude (EVM) is a system-level parameter that is specified for most advanced communication standards. EVM measurement often takes extensive test development efforts, tester resources, and long test times. EVM is analytically related to system impairments, which are typically measured in a production test i environment. Thus, EVM test can be eliminated from the test list if the relations between EVM and system impairments are derived independent of the circuit implementation and manufacturing process. In this work, the focus is on the WLAN standard, and deriving the relations between EVM and three of the most detrimental impairments for QAM/OFDM based systems (IQ imbalance, non-linearity, and noise). Having low cost test techniques for measuring the RF transceivers imperfections and being able to analytically compute EVM from the measured parameters is a complete test solution for RF transceivers. These techniques along with the proposed calibration method can be used in improving the yield by widening the pass/fail boundaries for transceivers imperfections. For all of the proposed methods, simulation and hardware measurements prove that the proposed techniques provide accurate characterization of RF transceivers.
ContributorsNassery, Afsaneh (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Synchronous buck converters have become the obvious choice of design for high efficiency voltage down-conversion applications and find wide scale usage in today's IC industry. The use of digital control in synchronous buck converters is becoming increasingly popular because of its associated advantages over traditional analog counterparts in terms of

Synchronous buck converters have become the obvious choice of design for high efficiency voltage down-conversion applications and find wide scale usage in today's IC industry. The use of digital control in synchronous buck converters is becoming increasingly popular because of its associated advantages over traditional analog counterparts in terms of design flexibility, reduced use of off-chip components, and better programmability to enable advanced controls. They also demonstrate better immunity to noise, enhances tolerance to the process, voltage and temperature (PVT) variations, low chip area and as a result low cost. It enables processing in digital domain requiring a need of analog-digital interfacing circuit viz. Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC). A Digital to Pulse Width Modulator (DPWM) acts as time domain DAC required in the control loop to modulate the ON time of the Power-MOSFETs. The accuracy and efficiency of the DPWM creates the upper limit to the steady state voltage ripple of the DC - DC converter and efficiency in low load conditions. This thesis discusses the prevalent architectures for DPWM in switched mode DC - DC converters. The design of a Hybrid DPWM is presented. The DPWM is 9-bit accurate and is targeted for a Synchronous Buck Converter with a switching frequency of 1.0 MHz. The design supports low power mode(s) for the buck converter in the Pulse Frequency Modulation (PFM) mode as well as other fail-safe features. The design implementation is digital centric making it robust across PVT variations and portable to lower technology nodes. Key target of the design is to reduce design time. The design is tested across large Process (+/- 3σ), Voltage (1.8V +/- 10%) and Temperature (-55.0 °C to 125 °C) and is in the process of tape-out.
ContributorsKumar, Amit (Author) / Bakkaloglu, Bertan (Thesis advisor) / Song, Hongjiang (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
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Description
This thesis describes the design process used in the creation of a two stage cellular power amplifier. A background for understanding amplifier linearity, device properties, and ACLR estimation is provided. An outline of the design goals is given with a focus on linearity with high efficiency. The full design is

This thesis describes the design process used in the creation of a two stage cellular power amplifier. A background for understanding amplifier linearity, device properties, and ACLR estimation is provided. An outline of the design goals is given with a focus on linearity with high efficiency. The full design is broken into smaller elements which are discussed in detail. The main contribution of this thesis is the description of a novel interstage matching network topology for increasing efficiency. Ultimately the full amplifier design is simulated and compared to the measured results and design goals. It was concluded that the design was successful, and used in a commercially available product.
ContributorsSpivey, Erin (Author) / Aberle, James T., 1961- (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
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Description
Doppler radar can be used to measure respiration and heart rate without contact and through obstacles. In this work, a Doppler radar architecture at 2.4 GHz and a new signal processing algorithm to estimate the respiration and heart rate are presented. The received signal is dominated by the transceiver noise,

Doppler radar can be used to measure respiration and heart rate without contact and through obstacles. In this work, a Doppler radar architecture at 2.4 GHz and a new signal processing algorithm to estimate the respiration and heart rate are presented. The received signal is dominated by the transceiver noise, LO phase noise and clutter which reduces the signal-to-noise ratio of the desired signal. The proposed architecture and algorithm are used to mitigate these issues and obtain an accurate estimate of the heart and respiration rate. Quadrature low-IF transceiver architecture is adopted to resolve null point problem as well as avoid 1/f noise and DC offset due to mixer-LO coupling. Adaptive clutter cancellation algorithm is used to enhance receiver sensitivity coupled with a novel Pattern Search in Noise Subspace (PSNS) algorithm is used to estimate respiration and heart rate. PSNS is a modified MUSIC algorithm which uses the phase noise to enhance Doppler shift detection. A prototype system was implemented using off-the-shelf TI and RFMD transceiver and tests were conduct with eight individuals. The measured results shows accurate estimate of the cardio pulmonary signals in low-SNR conditions and have been tested up to a distance of 6 meters.
ContributorsKhunti, Hitesh Devshi (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Bliss, Daniel (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
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Description
This thesis work mainly examined the stability and reliability issues of amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors under bias-illumination stress. Amorphous hydrogenated silicon has been the dominating material used in thin film transistors as a channel layer. However with the advent of modern high performance display technologies,

This thesis work mainly examined the stability and reliability issues of amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors under bias-illumination stress. Amorphous hydrogenated silicon has been the dominating material used in thin film transistors as a channel layer. However with the advent of modern high performance display technologies, it is required to have devices with better current carrying capability and better reproducibility. This brings the idea of new material for channel layer of these devices. Researchers have tried poly silicon materials, organic materials and amorphous mixed oxide materials as a replacement to conventional amorphous silicon layer. Due to its low price and easy manufacturing process, amorphous mixed oxide thin film transistors have become a viable option to replace the conventional ones in order to achieve high performance display circuits. But with new materials emerging, comes the challenge of reliability and stability issues associated with it. Performance measurement under bias stress and bias-illumination stress have been reported previously. This work proposes novel post processing low temperature long time annealing in optimum ambient in order to annihilate or reduce the defects and vacancies associated with amorphous material which lead to the instability or even the failure of the devices. Thin film transistors of a-IGZO has been tested for standalone illumination stress and bias-illumination stress before and after annealing. HP 4155B semiconductor parameter analyzer has been used to stress the devices and measure the output characteristics and transfer characteristics of the devices. Extra attention has been given about the effect of forming gas annealing on a-IGZO thin film. a-IGZO thin film deposited on silicon substrate has been tested for resistivity, mobility and carrier concentration before and after annealing in various ambient. Elastic Recoil Detection has been performed on the films to measure the amount of hydrogen atoms present in the film. Moreover, the circuit parameters of the thin film transistors has been extracted to verify the physical phenomenon responsible for the instability and failure of the devices. Parameters like channel resistance, carrier mobility, power factor has been extracted and variation of these parameters has been observed before and after the stress.
ContributorsRuhul Hasin, Muhammad (Author) / Alford, Terry L. (Thesis advisor) / Krause, Stephen (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
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Description
With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This

With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This thesis discusses one such block, the sub-ADC (Flash ADC), of the pipeline and sharing it with more than two of the parallel processing channels thereby reducing area and power and input load capacitance to each stage. This work presents a design of 'sub-ADC shared in a time-interleaved pipeline ADC' in the IBM 8HP process. It has been implemented with an offset-compensated, kickback-compensated, fast decision making (large input bandwidth) and low power comparator that forms the core part of the design.
ContributorsBikkina, Phaneendra Kumar (Author) / Barnaby, Hugh (Thesis advisor) / Mikkola, Esko (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
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Description
In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB)

In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time.
ContributorsKim, Kibeom (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Photovoltaic (PV) modules appear to have three classifications of failure: Infant mortality, normal-life failure, and end-of-life failure. Little is known of the end-of-life failures experienced by PV modules due to their inherent longevity. Accelerated Life Testing (ALT) has been at the crux of this lifespan prediction; however, without naturally failing

Photovoltaic (PV) modules appear to have three classifications of failure: Infant mortality, normal-life failure, and end-of-life failure. Little is known of the end-of-life failures experienced by PV modules due to their inherent longevity. Accelerated Life Testing (ALT) has been at the crux of this lifespan prediction; however, without naturally failing modules an accurate acceleration factor cannot be determined for use in ALT. By observing modules that have been aged in the field, a comparison can be made with modules undergoing accelerated testing. In this study an investigation on about 1900 aged (10-17 years) grid-tied PV modules installed in the desert climatic condition of Arizona was undertaken. The investigation was comprised of a check sheet that documented any visual defects and their severity, infrared (IR) scanning, and current-voltage (I-V) curve measurements. After data was collected on modules, an analysis was performed to classify the failure modes and to determine the annual performance degradation rates.
ContributorsSuleske, Adam Alfred (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Macia, Narciso (Committee member) / Arizona State University (Publisher)
Created2010