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- All Subjects: engineering
- Creators: Bakkaloglu, Bertan
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
Biosensors aiming at detection of target analytes, such as proteins, microbes, virus, and toxins, are widely needed for various applications including detection of chemical and biological warfare (CBW) agents, biomedicine, environmental monitoring, and drug screening. Surface Plasmon Resonance (SPR), as a surface-sensitive analytical tool, can very sensitively respond to minute changes of refractive index occurring adjacent to a metal film, offering detection limits up to a few ppt (pg/mL). Through SPR, the process of protein adsorption may be monitored in real-time, and transduced into an SPR angle shift. This unique technique bypasses the time-consuming, labor-intensive labeling processes, such as radioisotope and fluorescence labeling. More importantly, the method avoids the modification of the biomarker’s characteristics and behaviors by labeling that often occurs in traditional biosensors. While many transducers, including SPR, offer high sensitivity, selectivity is determined by the bio-receptors. In traditional biosensors, the selectivity is provided by bio-receptors possessing highly specific binding affinity to capture target analytes, yet their use in biosensors are often limited by their relatively-weak binding affinity with analyte, non-specific adsorption, need for optimization conditions, low reproducibility, and difficulties integrating onto the surface of transducers. In order to circumvent the use of bio-receptors, the competitive adsorption of proteins, termed the Vroman effect, is utilized in this work. The Vroman effect was first reported by Vroman and Adams in 1969. The competitive adsorption targeted here occurs among different proteins competing to adsorb to a surface, when more than one type of protein is present. When lower-affinity proteins are adsorbed on the surface first, they can be displaced by higher-affinity proteins arriving at the surface at a later point in time. Moreover, only low-affinity proteins can be displaced by high-affinity proteins, typically possessing higher molecular weight, yet the reverse sequence does not occur. The SPR biosensor based on competitive adsorption is successfully demonstrated to detect fibrinogen and thyroglobulin (Tg) in undiluted human serum and copper ions in drinking water through the denatured albumin.
ContributorsWang, Ran (Author) / Chae, Junseok (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tsow, Tsing (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2015
Description
Two-dimensional transition metal dichalcogenides (TMDCs) such as
molybdenum disulfide (MoS2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2) and tungsten diselenide (WSe2) are attractive for use in biotechnology, optical and electronics devices due to their promising and tunable electrical, optical and chemical properties. To fulfill the variety of requirements for different applications, chemical treatment methods are developed to tune their properties. In this dissertation, plasma treatment, chemical doping and functionalization methods have been applied to tune the properties of TMDCs. First, plasma treatment of TMDCs results in doping and generation of defects, as well as the synthesis of transition metal oxides (TMOs) with rolled layers that have increased surface-to-volume ratio and are promising for electrochemical applications. Second, chemical functionalization is another powerful approach for tuning the properties of TMDCs for use in many applications. To covalently functionalize the basal planes of TMDCs, previous reports begin with harsh treatments like lithium intercalation that disrupt the structure and lead to a phase transformation from semiconducting to metallic. Instead, this work demonstrates the direct covalent functionalization of semiconducting MoS2 using aryl diazonium salts without lithium treatments. It preserves the structure and semiconducting nature of MoS2, results in covalent C-S bonds on basal planes and enables different functional groups to be tethered to the MoS2 surface via the diazonium salts. The attachment of fluorescent proteins has been used as a demonstration and it suggests future applications in biology and biosensing. The effects of the covalent functionalization on the electronic transport properties of MoS2 were then studied using field effect transistor (FET) devices.
molybdenum disulfide (MoS2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2) and tungsten diselenide (WSe2) are attractive for use in biotechnology, optical and electronics devices due to their promising and tunable electrical, optical and chemical properties. To fulfill the variety of requirements for different applications, chemical treatment methods are developed to tune their properties. In this dissertation, plasma treatment, chemical doping and functionalization methods have been applied to tune the properties of TMDCs. First, plasma treatment of TMDCs results in doping and generation of defects, as well as the synthesis of transition metal oxides (TMOs) with rolled layers that have increased surface-to-volume ratio and are promising for electrochemical applications. Second, chemical functionalization is another powerful approach for tuning the properties of TMDCs for use in many applications. To covalently functionalize the basal planes of TMDCs, previous reports begin with harsh treatments like lithium intercalation that disrupt the structure and lead to a phase transformation from semiconducting to metallic. Instead, this work demonstrates the direct covalent functionalization of semiconducting MoS2 using aryl diazonium salts without lithium treatments. It preserves the structure and semiconducting nature of MoS2, results in covalent C-S bonds on basal planes and enables different functional groups to be tethered to the MoS2 surface via the diazonium salts. The attachment of fluorescent proteins has been used as a demonstration and it suggests future applications in biology and biosensing. The effects of the covalent functionalization on the electronic transport properties of MoS2 were then studied using field effect transistor (FET) devices.
ContributorsChu, Ximo (Author) / Wang, Qing Hua (Thesis advisor) / Sieradzki, Karl (Committee member) / Green, Alexander (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2018
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.
ContributorsHabibiMehr, Payam (Author) / Thornton, Trevor John (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Formicone, Gabriele (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2019
Description
Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
ContributorsBakliwal, Priyanka (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
Description
High photoluminescence (PL) quantum yields reported from amorphous (a-Si) and crystalline (c-Si) nanoparticles have opened up lots of possibilities for use of silicon in optical applications such as light emitting diodes (LEDs), photonics and solar cells with added processing and cost benefits. However, the PL response and the mechanisms behind it are highly dependent on the matrix in which the nanoparticles are grown and on the growth method. While, the bottom-up approach for deposition of free standing nanoparticles seem to be perfectly suited for large area deposition for LED and solar cell applications, the dominant growth techniques (laser ablation and pyrolysis) have been shown to suffer from limitations in control over size distribution of nanoparticles and the requirement of equipment capable of withstanding high temperature. This led to the exploration of plasma based synthesis methods in this work.
Towards this effort, the development and automation of a novel tool “Anny” for synthesis of silicon nanoparticles using non-thermal plasma chamber is reported. These nanoparticles are then accelerated due to choked flow through a nozzle leading to substrate independent deposition. The nanoparticle properties are characterized against precursor gas flow rates and RF power to identify the optimum growth conditions for a stable, continuous deposition. It is found that amorphous nanoparticles offer a wide variety of chamber conditions for growth with a high throughput, stable plasma for continuous, long term operations.
The quantum confinement model for crystalline and spatial confinement models for amorphous nanoparticles in our size regime (6-8nm) are suggested for free standing nanoparticles and we report a high PL output from well passivated amorphous nanoparticles.
The PL output and its dependence on stability of surface hydrogen passivation is explored using Fourier Transform Infrared spectroscopy (FTIR). It is shown that the amorphous nanoparticles have a better and more stable passivation compared to crystalline nanoparticles grown under similar conditions. Hence, we show a-Si nanoparticles as exciting alternatives for optical applications to c-Si nanoparticles.
Towards this effort, the development and automation of a novel tool “Anny” for synthesis of silicon nanoparticles using non-thermal plasma chamber is reported. These nanoparticles are then accelerated due to choked flow through a nozzle leading to substrate independent deposition. The nanoparticle properties are characterized against precursor gas flow rates and RF power to identify the optimum growth conditions for a stable, continuous deposition. It is found that amorphous nanoparticles offer a wide variety of chamber conditions for growth with a high throughput, stable plasma for continuous, long term operations.
The quantum confinement model for crystalline and spatial confinement models for amorphous nanoparticles in our size regime (6-8nm) are suggested for free standing nanoparticles and we report a high PL output from well passivated amorphous nanoparticles.
The PL output and its dependence on stability of surface hydrogen passivation is explored using Fourier Transform Infrared spectroscopy (FTIR). It is shown that the amorphous nanoparticles have a better and more stable passivation compared to crystalline nanoparticles grown under similar conditions. Hence, we show a-Si nanoparticles as exciting alternatives for optical applications to c-Si nanoparticles.
ContributorsGarg, Prateek (Author) / Holman, Zachary C (Thesis advisor) / Zhang, Yong H (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2015
Description
The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
ContributorsDesai, Chirag (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016
Description
Lithium ion batteries have emerged as the most popular energy storage system, but they pose safety issues under extreme temperatures or in the event of a thermal runaway. Lithium ion batteries with inorganic separators offer the advantage of safer operation. An inorganic separator for lithium ion battery was prepared by an improved method of blade coating α-Al2O3 slurry directly on the electrode followed by drying. The improved separator preparation involves a twice-coating process instead of coating the slurry all at once in order to obtain a thin (~40 µm) and uniform coat. It was also found that α-Al2O3 powder with particle size greater than the pore size in the electrode is preferable for obtaining a separator with 40 µm thickness and consistent cell performance. Unlike state-of-the-art polyolefin separators such as polypropylene (PP) which are selectively wettable with only certain electrolytes, the excellent electrolyte solvent wettability of α-Al2O3 allows the coated alumina separator to function with different electrolytes. The coated α-Al2O3 separator has a much higher resistance to temperature effects than its polyolefin counterparts, retaining its dimensional integrity at temperatures as high as 200ºC. This eliminates the possibility of a short circuit during thermal runaway. Lithium ion batteries assembled as half-cells and full cells with coated α-Al2O3 separator exhibit electrochemical performance comparable with that of polyolefin separators at room temperature. However, the cells with coated alumina separator shows better cycling performance under extreme temperatures in the temperature range of -30°C to 60°C. Therefore, the coated α-Al2O3 separator is very promising for application in safe lithium-ion batteries.
ContributorsSharma, Gaurav (Author) / Lin, Jerry Y.S. (Thesis advisor) / Chan, Candace (Committee member) / Kannan, Arunachala (Committee member) / Arizona State University (Publisher)
Created2016