Matching Items (17)
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- All Subjects: engineering
- All Subjects: Integrated circuits
- Creators: Kitchen, Jennifer
Description
Isolated DC/DC converters are used to provide electrical isolation between two supply domain systems. A fully integrated isolated DC/DC converter having no board-level components and fabricated using standard integrated circuits (IC) process is highly desirable in order to increase the system reliability and reduce costs. The isolation between the low-voltage side and high-voltage side of the converter is realized by a transformer that transfers energy while blocking the DC loop. The resonant mode power oscillator is used to enable high efficiency power transfer. The on-chip transformer is expected to have high coil inductance, high quality factors and high coupling coefficient to reduce the loss in the oscillation. The performance of a transformer is highly dependent on the vertical structure, horizontal geometry and other indispensable structures that make it compatible with the IC process such as metal fills and patterned ground shield (PGS). With the help of three-dimensional (3-D) electro-magnetic (EM) simulation software, the 3-D transformer model is simulated and the simulation result is got with high accuracy.
In this thesis an on-chip transformer for a fully integrated DC/DC converter using standard IC process is developed. Different types of transformers are modeled and simulated in HFSS. The performances are compared to select the optimum design. The effects of the additional structures including PGS and metal fills are also simulated. The transformer is tested with a network analyzer and the testing results show a good consistency with the simulation results when taking the chip traces, printed circuit board (PCB) traces, bond wires and SMA connectors into account.
In this thesis an on-chip transformer for a fully integrated DC/DC converter using standard IC process is developed. Different types of transformers are modeled and simulated in HFSS. The performances are compared to select the optimum design. The effects of the additional structures including PGS and metal fills are also simulated. The transformer is tested with a network analyzer and the testing results show a good consistency with the simulation results when taking the chip traces, printed circuit board (PCB) traces, bond wires and SMA connectors into account.
ContributorsZhao, Yao (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
ContributorsPadala, Sudheer (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Power Management circuits are employed in almost all electronic equipment and they have energy storage elements (capacitors and inductors) as building blocks along with other active circuitry. Power management circuits employ feedback to achieve good load and line regulation. The feedback loop is designed at an operating point and component values are chosen to meet that design requirements. But the capacitors and inductors are subject to variations due to temperature, aging and load stress. Due to these variations, the feedback loop can cross its robustness margins and can lead to degraded performance and potential instability. Another issue in power management circuits is the measurement of their frequency response for stability assessment. The standard techniques used in production test environment require expensive measurement equipment (Network Analyzer) and time. These two issues of component variations and frequency response measurement can be addressed if the frequency response of the power converter is used as measure of component (capacitor and inductor) variations. So, a single solution of frequency response measurement solves both the issues. This work examines system identification (frequency response measurement) of power management circuits based on cross correlation technique and proposes the use of switched capacitor correlator for this purpose. A switched capacitor correlator has been designed and used in the system identification of Linear and Switching regulators. The obtained results are compared with the standard frequency response measurement methods of power converters.
ContributorsMalladi, Venkata Naga Koushik (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.
ContributorsHabibiMehr, Payam (Author) / Thornton, Trevor John (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Formicone, Gabriele (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2019
Description
The Phoenix CubeSat is a 3U Earth imaging CubeSat which will take infrared (IR) photos of cities in the United Stated to study the Urban Heat Island Effect, (UHI) from low earth orbit (LEO). It has many different components that need to be powered during the life of its mission. The only power source during the mission will be its solar panels. It is difficult to calculate power generation from solar panels by hand because of the different orientations the satellite will be positioned in during orbit; therefore, simulation will be used to produce power generation data. Knowing how much power is generated is integral to balancing the power budget, confirming whether there is enough power for all the components, and knowing whether there will be enough power in the batteries during eclipse. This data will be used to create an optimal design for the Phoenix CubeSat to accomplish its mission.
ContributorsBarakat, Raymond John (Author) / White, Daniel (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2017-05
Description
Current technology does not allow for the full amount of power produced by solar arrays (PV) on spacecraft to be utilized. The arrays are designed with non-reconfigurable architectures and sent on fifteen to twenty year long missions. They cannot be changed once they are in space, so the arrays are designed for the end of life. Throughout their lifetime, solar arrays can degrade in power producing capabilities anywhere from 20% to 50%. Because there is such a drastic difference in the beginning and end of life power production, and because they cannot be reconfigured, a new design has been found necessary in order to increase power production. Reconfiguration allows the solar arrays to achieve maximum power producing capabilities at both the beginning and end of their lives. With the potential to increase power production by 50%, the reconfiguration design consists of a switching network to be able to utilize any combination of cells. The design for reconfiguration must meet the power requirements of the solar array. This thesis will explore different designs for reconfiguration, as well as possible switches for implementation. It will also review other methods to increase power production, as well as discuss future work in this field.
ContributorsJohnson, Everett Hope (Author) / Kitchen, Jennifer (Thesis director) / Ozev, Sule (Committee member) / School of International Letters and Cultures (Contributor) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
ContributorsBakliwal, Priyanka (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
Description
A single solar cell provides close to 0.5 V output at its maximum power point, which is very
low for any electronic circuit to operate. To get rid of this problem, traditionally multiple
solar cells are connected in series to get higher voltage. The disadvantage of this approach
is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can
result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT)
at single solar cell level is the most efficient way to extract power from solar cell.
Power Management IC (MPIC) used to extract power from single solar cell, needs to
start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area
overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an
auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input.
The auxiliary supply powers up a MPPT converter followed by a regulated converter. At
the start up both the converters operate at 100 kHz clock with 80% duty cycle and system
output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up
circuit is turned off and the supply voltage for both the converters is derived from the system
output itself. In steady-state condition the system output is regulated to 3.0 V.
A fully integrated analog MPPT technique is proposed to extract maximum power from
the solar cell. This technique does not require Analog to Digital Converter (ADC) and
Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed
MPPT techniques includes a switch capacitor based power sensor which senses current of
boost converter without using any sense resistor. A complete system is designed which
starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output.
low for any electronic circuit to operate. To get rid of this problem, traditionally multiple
solar cells are connected in series to get higher voltage. The disadvantage of this approach
is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can
result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT)
at single solar cell level is the most efficient way to extract power from solar cell.
Power Management IC (MPIC) used to extract power from single solar cell, needs to
start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area
overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an
auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input.
The auxiliary supply powers up a MPPT converter followed by a regulated converter. At
the start up both the converters operate at 100 kHz clock with 80% duty cycle and system
output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up
circuit is turned off and the supply voltage for both the converters is derived from the system
output itself. In steady-state condition the system output is regulated to 3.0 V.
A fully integrated analog MPPT technique is proposed to extract maximum power from
the solar cell. This technique does not require Analog to Digital Converter (ADC) and
Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed
MPPT techniques includes a switch capacitor based power sensor which senses current of
boost converter without using any sense resistor. A complete system is designed which
starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output.
ContributorsSingh, Shrikant (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
Description
Since the inception of Internet of Things (IoT) framework, the amount of interaction between electronic devices has tremendously increased and the ease of implementing software between such devices has bettered. Such data exchange between devices, whether between Node to Server or Node to Node, has paved way for creating new business models. Wireless Video Sensor Network Platforms are being used to monitor and understand the surroundings better. Both hardware and software supporting such devices have become much smaller and yet stronger to enable these. Specifically, the invention of better software that enable Wireless data transfer have become more simpler and lightweight technologies such as HTML5 for video rendering, Common Gateway Interface(CGI) scripts enabling interactions between client and server and WebRTC from Google for peer to peer interactions. The role of web browsers in enabling these has been vastly increasing.
Although HTTP is the most reliable and consistent data transfer protocol for such interactions, the most important underlying challenge with such platforms is the performance based on power consumption and latency in data transfer.
In the scope of this thesis, two applications using CGI and WebRTC for data transfer over HTTP will be presented and the power consumption by the peripherals in transmitting the data and the possible implications for those will be discussed.
Although HTTP is the most reliable and consistent data transfer protocol for such interactions, the most important underlying challenge with such platforms is the performance based on power consumption and latency in data transfer.
In the scope of this thesis, two applications using CGI and WebRTC for data transfer over HTTP will be presented and the power consumption by the peripherals in transmitting the data and the possible implications for those will be discussed.
ContributorsRentala, Sri Harsha (Author) / Reisslein, Martin (Thesis advisor) / Kitchen, Jennifer (Committee member) / McGarry, Michael (Committee member) / Arizona State University (Publisher)
Created2016