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- All Subjects: engineering
- Genre: Academic theses
- Genre: Masters Thesis
- Creators: Bakkaloglu, Bertan
- Creators: Srinivasan, Devarajan
- Member of: Theses and Dissertations
Description
Potential induced degradation (PID) due to high system voltages is one of the major degradation mechanisms in photovoltaic (PV) modules, adversely affecting their performance due to the combined effects of the following factors: system voltage, superstrate/glass surface conductivity, encapsulant conductivity, silicon nitride anti-reflection coating property and interface property (glass/encapsulant; encapsulant/cell; encapsulant/backsheet). Previous studies carried out at ASU's Photovoltaic Reliability Laboratory (ASU-PRL) showed that only negative voltage bias (positive grounded systems) adversely affects the performance of commonly available crystalline silicon modules. In previous studies, the surface conductivity of the glass surface was obtained using either conductive carbon layer extending from the glass surface to the frame or humidity inside an environmental chamber. This thesis investigates the influence of glass surface conductivity disruption on PV modules. In this study, conductive carbon was applied only on the module's glass surface without extending to the frame and the surface conductivity was disrupted (no carbon layer) at 2cm distance from the periphery of frame inner edges. This study was carried out under dry heat at two different temperatures (60 °C and 85 °C) and three different negative bias voltages (-300V, -400V, and -600V). To replicate closeness to the field conditions, half of the selected modules were pre-stressed under damp heat for 1000 hours (DH 1000) and the remaining half under 200 hours of thermal cycling (TC 200). When the surface continuity was disrupted by maintaining a 2 cm gap from the frame to the edge of the conductive layer, as demonstrated in this study, the degradation was found to be absent or negligibly small even after 35 hours of negative bias at elevated temperatures. This preliminary study appears to indicate that the modules could become immune to PID losses if the continuity of the glass surface conductivity is disrupted at the inside boundary of the frame. The surface conductivity of the glass, due to water layer formation in a humid condition, close to the frame could be disrupted just by applying a water repelling (hydrophobic) but high transmittance surface coating (such as Teflon) or modifying the frame/glass edges with water repellent properties.
ContributorsTatapudi, Sai Ravi Vasista (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2012
Description
While the piezoelectric effect has been around for some time, it has only recently caught interest as a potential sustainable energy harvesting device. Piezoelectric energy harvesting has been developed for shoes and panels, but has yet to be integrated into a marketable bicycle tire. For this thesis, the development and feasibility of a piezoelectric tire was done. This includes the development of a circuit that incorporates piezoceramic elements, energy harvesting circuitry, and an energy storage device. A single phase circuit was designed using an ac-dc diode rectifier. An electrolytic capacitor was used as the energy storage device. A financial feasibility was also done to determine targets for manufacturing cost and sales price. These models take into account market trends for high performance tires, economies of scale, and the possibility of government subsidies. This research will help understand the potential for the marketability of a piezoelectric energy harvesting tire that can create electricity for remote use. This study found that there are many obstacles that must be addressed before a piezoelectric tire can be marketed to the general public. The power output of this device is miniscule compared to an alkaline battery. In order for this device to approach the power output of an alkaline battery the weight of the device would also become an issue. Additionally this device is very costly compared to the average bicycle tire. Lastly, this device is extreme fragile and easily broken. In order for this device to become marketable the issues of power output, cost, weight, and durability must all be successfully overcome.
ContributorsMalotte, Christopher (Author) / Madakannan, Arunachalanadar (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2012
Description
ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed.
ContributorsKumar, Sushil (Author) / Clark, Lawrence (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Characterization and analysis of long term field aged photovoltaic modules and encapsulant materials
Description
Photovoltaic (PV) module degradation is a well-known issue, however understanding the mechanistic pathways in which modules degrade is still a major task for the PV industry. In order to study the mechanisms responsible for PV module degradation, the effects of these degradation mechanisms must be quantitatively measured to determine the severity of each degradation mode. In this thesis multiple modules from three climate zones (Arizona, California and Colorado) were investigated for a single module glass/polymer construction (Siemens M55) to determine the degree to which they had degraded, and the main factors that contributed to that degradation. To explain the loss in power, various nondestructive and destructive techniques were used to indicate possible causes of loss in performance. This is a two-part thesis. Part 1 presents non-destructive test results and analysis and Part 2 presents destructive test results and analysis.
ContributorsChicca, Matthew (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Srinivasan, Devarajan (Committee member) / Arizona State University (Publisher)
Created2015
Description
Biosensors aiming at detection of target analytes, such as proteins, microbes, virus, and toxins, are widely needed for various applications including detection of chemical and biological warfare (CBW) agents, biomedicine, environmental monitoring, and drug screening. Surface Plasmon Resonance (SPR), as a surface-sensitive analytical tool, can very sensitively respond to minute changes of refractive index occurring adjacent to a metal film, offering detection limits up to a few ppt (pg/mL). Through SPR, the process of protein adsorption may be monitored in real-time, and transduced into an SPR angle shift. This unique technique bypasses the time-consuming, labor-intensive labeling processes, such as radioisotope and fluorescence labeling. More importantly, the method avoids the modification of the biomarker’s characteristics and behaviors by labeling that often occurs in traditional biosensors. While many transducers, including SPR, offer high sensitivity, selectivity is determined by the bio-receptors. In traditional biosensors, the selectivity is provided by bio-receptors possessing highly specific binding affinity to capture target analytes, yet their use in biosensors are often limited by their relatively-weak binding affinity with analyte, non-specific adsorption, need for optimization conditions, low reproducibility, and difficulties integrating onto the surface of transducers. In order to circumvent the use of bio-receptors, the competitive adsorption of proteins, termed the Vroman effect, is utilized in this work. The Vroman effect was first reported by Vroman and Adams in 1969. The competitive adsorption targeted here occurs among different proteins competing to adsorb to a surface, when more than one type of protein is present. When lower-affinity proteins are adsorbed on the surface first, they can be displaced by higher-affinity proteins arriving at the surface at a later point in time. Moreover, only low-affinity proteins can be displaced by high-affinity proteins, typically possessing higher molecular weight, yet the reverse sequence does not occur. The SPR biosensor based on competitive adsorption is successfully demonstrated to detect fibrinogen and thyroglobulin (Tg) in undiluted human serum and copper ions in drinking water through the denatured albumin.
ContributorsWang, Ran (Author) / Chae, Junseok (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tsow, Tsing (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2015
Description
Encapsulant is a key packaging component of photovoltaic (PV) modules, which protects the solar cell from physical, environmental and electrical damages. Ethylene-vinyl acetate (EVA) is one of the major encapsulant materials used in the PV industry. This work focuses on indoor accelerated ultraviolet (UV) stress testing and characterization to investigate the EVA discoloration and delamination in PV modules by using various non-destructive characterization techniques, including current-voltage (IV) measurements, UV fluorescence (UVf) and colorimetry measurements. Mini-modules with glass/EVA/cell/EVA/backsheet construction were fabricated in the laboratory with two types of EVA, UV-cut EVA (UVC) and UV-pass EVA (UVP).
The accelerated UV testing was performed in a UV chamber equipped with UV lights at an ambient temperature of 50°C, little or no humidity and total UV dosage of 400 kWh/m2. The mini-modules were maintained at three different temperatures through UV light heating by placing different thickness of thermal insulation sheets over the backsheet. Also, prior to thermal insulation sheet placement, the backsheet and laminate edges were fully covered with aluminum tape to prevent oxygen diffusion into the module and hence the photobleaching reaction.
The characterization results showed that mini-modules with UV-cut EVA suffered from discoloration while the modules with UV-pass EVA suffered from delamination. UVf imaging technique has the capability to identify the discoloration region in the UVC modules in the very early stage when the discoloration is not visible to the naked eyes, whereas Isc measurement is unable to measure the performance loss until the color becomes visibly darker. YI also provides the direct evidence of yellowing in the encapsulant. As expected, the extent of degradation due to discoloration increases with the increase in module temperature. The Isc loss is dictated by both the regions – discolored area at the center and non-discolored area at the cell edges, whereas the YI is only determined at the discolored region due to low probe area. This led to the limited correlation between Isc and YI in UVC modules.
In case of UVP modules, UV radiation has caused an adverse impact on the interfacial adhesion between the EVA and solar cell, which was detected from UVf images and severe Isc loss. No change in YI confirms that the reason for Isc loss is not due to yellowing but the delamination.
Further, the activation energy of encapsulant discoloration was estimated by using Arrhenius model on two types of data, %Isc drop and ΔYI. The Ea determined from the change in YI data for the EVA encapsulant discoloration reaction without the influence of oxygen and humidity is 0.61 eV. Based on the activation energy determined in this work and hourly weather data of any site, the degradation rate for the encaspulant browning mode can be estimated.
The accelerated UV testing was performed in a UV chamber equipped with UV lights at an ambient temperature of 50°C, little or no humidity and total UV dosage of 400 kWh/m2. The mini-modules were maintained at three different temperatures through UV light heating by placing different thickness of thermal insulation sheets over the backsheet. Also, prior to thermal insulation sheet placement, the backsheet and laminate edges were fully covered with aluminum tape to prevent oxygen diffusion into the module and hence the photobleaching reaction.
The characterization results showed that mini-modules with UV-cut EVA suffered from discoloration while the modules with UV-pass EVA suffered from delamination. UVf imaging technique has the capability to identify the discoloration region in the UVC modules in the very early stage when the discoloration is not visible to the naked eyes, whereas Isc measurement is unable to measure the performance loss until the color becomes visibly darker. YI also provides the direct evidence of yellowing in the encapsulant. As expected, the extent of degradation due to discoloration increases with the increase in module temperature. The Isc loss is dictated by both the regions – discolored area at the center and non-discolored area at the cell edges, whereas the YI is only determined at the discolored region due to low probe area. This led to the limited correlation between Isc and YI in UVC modules.
In case of UVP modules, UV radiation has caused an adverse impact on the interfacial adhesion between the EVA and solar cell, which was detected from UVf images and severe Isc loss. No change in YI confirms that the reason for Isc loss is not due to yellowing but the delamination.
Further, the activation energy of encapsulant discoloration was estimated by using Arrhenius model on two types of data, %Isc drop and ΔYI. The Ea determined from the change in YI data for the EVA encapsulant discoloration reaction without the influence of oxygen and humidity is 0.61 eV. Based on the activation energy determined in this work and hourly weather data of any site, the degradation rate for the encaspulant browning mode can be estimated.
ContributorsDolia, Kshitiz (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Green, Matthew (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Arizona State University (Publisher)
Created2018
Description
Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
ContributorsHegde, Ashwath (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2018
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018