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- All Subjects: engineering
- Genre: Academic theses
- Genre: Masters Thesis
- Creators: Bakkaloglu, Bertan
- Creators: Mignolet, Marc
- Member of: Theses and Dissertations
Description
ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed.
ContributorsKumar, Sushil (Author) / Clark, Lawrence (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
High Pressure Superheater 1 (HPSH1) is the first heat exchange tube bank inside the Heat Recovery Steam Generator (HRSG) to encounter exhaust flue gas from the gas turbine of a Combined Cycle Power Plant. Steam flowing through the HPSH1 gains heat from the flue gas prior to entering the steam turbine. During cold start-ups, rapid temperature changes in operating condition give rise to significant temperature gradients in the thick-walled components of HPSH1 (manifolds, links, and headers). These temperature gradients produce thermal-structural stresses in the components. The resulting high cycle fatigue is a major concern as this can lead to premature failure of the components. The main objective of this project was to address the thermal-structural stress field induced in HPSH1 during a typical cold start-up transient. To this end, computational fluid dynamics (CFD) was used to carry out the thermal-fluid analysis of HPSH1. The calculated temperature distributions in the component walls were the primary inputs for the finite element (FEA) model that performed structural analysis. Thermal-structural analysis was initially carried out at full-load steady state condition in order to gain confidence in the CFD and FEA methodologies. Results of the full-load steady state thermal-fluid analysis were found in agreement with the temperature values measured at specific locations on the outer surfaces of the inlet links and outlet manifold. It was found from the subsequent structural analysis that peak effective stresses were located at the connecting regions of the components and were well below the allowed stress values. Higher temperature differences were observed between the thick-walled HPSH1 components during the cold start-up transient as compared to the full-load steady state operating condition. This was because of the rapid temperature changes that occurred, especially in the steam temperature at the HPSH1 entry, and the different rates of heating or cooling for components with different wall thicknesses. Results of the transient thermal-fluid analysis will be used in future to perform structural analysis of the HPSH1. The developed CFD and FEA models are capable of analyzing various other transients (e.g., hot start-up and shut-down) and determine their influence on the durability of plant components.
ContributorsHardeep Singh (Author) / Roy, Ramendra P. (Thesis advisor) / Lee, Taewoo (Thesis advisor) / Mignolet, Marc (Committee member) / Arizona State University (Publisher)
Created2012
Description
This dissertation presents methods for addressing research problems that currently can only adequately be solved using Quality Reliability Engineering (QRE) approaches especially accelerated life testing (ALT) of electronic printed wiring boards with applications to avionics circuit boards. The methods presented in this research are generally applicable to circuit boards, but the data generated and their analysis is for high performance avionics. Avionics equipment typically requires 20 years expected life by aircraft equipment manufacturers and therefore ALT is the only practical way of performing life test estimates. Both thermal and vibration ALT induced failure are performed and analyzed to resolve industry questions relating to the introduction of lead-free solder product and processes into high reliability avionics. In chapter 2, thermal ALT using an industry standard failure machine implementing Interconnect Stress Test (IST) that simulates circuit board life data is compared to real production failure data by likelihood ratio tests to arrive at a mechanical theory. This mechanical theory results in a statistically equivalent energy bound such that failure distributions below a specific energy level are considered to be from the same distribution thus allowing testers to quantify parameter setting in IST prior to life testing. In chapter 3, vibration ALT comparing tin-lead and lead-free circuit board solder designs involves the use of the likelihood ratio (LR) test to assess both complete failure data and S-N curves to present methods for analyzing data. Failure data is analyzed using Regression and two-way analysis of variance (ANOVA) and reconciled with the LR test results that indicating that a costly aging pre-process may be eliminated in certain cases. In chapter 4, vibration ALT for side-by-side tin-lead and lead-free solder black box designs are life tested. Commercial models from strain data do not exist at the low levels associated with life testing and need to be developed because testing performed and presented here indicate that both tin-lead and lead-free solders are similar. In addition, earlier failures due to vibration like connector failure modes will occur before solder interconnect failures.
ContributorsJuarez, Joseph Moses (Author) / Montgomery, Douglas C. (Thesis advisor) / Borror, Connie M. (Thesis advisor) / Gel, Esma (Committee member) / Mignolet, Marc (Committee member) / Pan, Rong (Committee member) / Arizona State University (Publisher)
Created2012
Description
Biosensors aiming at detection of target analytes, such as proteins, microbes, virus, and toxins, are widely needed for various applications including detection of chemical and biological warfare (CBW) agents, biomedicine, environmental monitoring, and drug screening. Surface Plasmon Resonance (SPR), as a surface-sensitive analytical tool, can very sensitively respond to minute changes of refractive index occurring adjacent to a metal film, offering detection limits up to a few ppt (pg/mL). Through SPR, the process of protein adsorption may be monitored in real-time, and transduced into an SPR angle shift. This unique technique bypasses the time-consuming, labor-intensive labeling processes, such as radioisotope and fluorescence labeling. More importantly, the method avoids the modification of the biomarker’s characteristics and behaviors by labeling that often occurs in traditional biosensors. While many transducers, including SPR, offer high sensitivity, selectivity is determined by the bio-receptors. In traditional biosensors, the selectivity is provided by bio-receptors possessing highly specific binding affinity to capture target analytes, yet their use in biosensors are often limited by their relatively-weak binding affinity with analyte, non-specific adsorption, need for optimization conditions, low reproducibility, and difficulties integrating onto the surface of transducers. In order to circumvent the use of bio-receptors, the competitive adsorption of proteins, termed the Vroman effect, is utilized in this work. The Vroman effect was first reported by Vroman and Adams in 1969. The competitive adsorption targeted here occurs among different proteins competing to adsorb to a surface, when more than one type of protein is present. When lower-affinity proteins are adsorbed on the surface first, they can be displaced by higher-affinity proteins arriving at the surface at a later point in time. Moreover, only low-affinity proteins can be displaced by high-affinity proteins, typically possessing higher molecular weight, yet the reverse sequence does not occur. The SPR biosensor based on competitive adsorption is successfully demonstrated to detect fibrinogen and thyroglobulin (Tg) in undiluted human serum and copper ions in drinking water through the denatured albumin.
ContributorsWang, Ran (Author) / Chae, Junseok (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tsow, Tsing (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2015
Description
The stability of nanocrystalline microstructural features allows structural materials to be synthesized and tested in ways that have heretofore been pursued only on a limited basis, especially under dynamic loading combined with temperature effects. Thus, a recently developed, stable nanocrystalline alloy is analyzed here for quasi-static (<100 s-1) and dynamic loading (103 to 104 s-1) under uniaxial compression and tension at multiple temperatures ranging from 298-1073 K. After mechanical tests, microstructures are analyzed and possible deformation mechanisms are proposed. Following this, strain and strain rate history effects on mechanical behavior are analyzed using a combination of quasi-static and dynamic strain rate Bauschinger testing. The stable nanocrystalline material is found to exhibit limited flow stress increase with increasing strain rate as compared to that of both pure, coarse grained and nanocrystalline Cu. Further, the material microstructural features, which includes Ta nano-dispersions, is seen to pin dislocation at quasi-static strain rates, but the deformation becomes dominated by twin nucleation at high strain rates. These twins are pinned from further growth past nucleation by the Ta nano-dispersions. Testing of thermal and load history effects on the mechanical behavior reveals that when thermal energy is increased beyond 200 °C, an upturn in flow stress is present at strain rates below 104 s-1. However, in this study, this simple assumption, established 50-years ago, is shown to break-down when the average grain size and microstructural length-scale is decreased and stabilized below 100nm. This divergent strain-rate behavior is attributed to a unique microstructure that alters slip-processes and their interactions with phonons; thus enabling materials response with a constant flow-stress even at extreme conditions. Hence, the present study provides a pathway for designing and synthesizing a new-level of tough and high-energy absorbing materials.
ContributorsTurnage, Scott Andrew (Author) / Solanki, Kiran N (Thesis advisor) / Rajagopalan, Jagannathan (Committee member) / Peralta, Pedro (Committee member) / Darling, Kristopher A (Committee member) / Mignolet, Marc (Committee member) / Arizona State University (Publisher)
Created2017
Description
Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
ContributorsHegde, Ashwath (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2018
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
This paper describes an effort to bring wing structural stiffness and aeroelastic considerations early in the conceptual design process with an automated tool. Stiffness and aeroelasticity can be well represented with a stochastic model during conceptual design because of the high level of uncertainty and variability in wing non-structural mass such as fuel loading and control surfaces. To accomplish this, an improvement is made to existing design tools utilizing rule based automated design to generate wing torque box geometry from a specific wing outer mold-line. Simple analysis on deflection and inferred stiffness shows how early conceptual design choices can strongly impact the stiffness of the structure. The impacts of design choices and how the buckling constraints drive structural weight in particular examples are discussed. The model is then carried further to include a finite element model (FEM) to analyze resulting mode shapes and frequencies for use in aeroelastic analysis. The natural frequencies of several selected wing torque boxes across a range of loading cases are compared.
ContributorsMiskin, Daniel L (Author) / Takahashi, Timothy T (Thesis advisor) / Mignolet, Marc (Committee member) / Murthy, Raghavendra (Committee member) / Arizona State University (Publisher)
Created2018