Matching Items (20)
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- All Subjects: engineering
- Creators: Bakkaloglu, Bertan
Description
Automated vehicles are becoming more prevalent in the modern world. Using platoons of automated vehicles can have numerous benefits including increasing the safety of drivers as well as streamlining roadway operations. How individual automated vehicles within a platoon react to each other is essential to creating an efficient method of travel. This paper looks at two individual vehicles forming a platoon and tracks the time headway between the two. Several speed profiles are explored for the following vehicle including a triangular and trapezoidal speed profile. It is discovered that a safety violation occurs during platoon formation where the desired time headway between the vehicles is violated. The aim of this research is to explore if this violation can be eliminated or reduced through utilization of different speed profiles.
ContributorsLarson, Kurt Gregory (Author) / Lou, Yingyan (Thesis director) / Chen, Yan (Committee member) / Civil, Environmental and Sustainable Eng Program (Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Recurring incidents between pedestrians, bicycles, and vehicles at the intersection of Rural Road and Spence Avenue led to a team of students conducting their own investigation into the current conditions and analyzing a handful of alternatives. An extension of an industry-standard technique was used to build a control case which alternatives would be compared to. Four alternatives were identified, and the two that could be modeled in simulation software were both found to be technically feasible in the preliminary analysis.
ContributorsFellows, Christopher Lee (Author) / Lou, Yingyan (Thesis director) / Zhou, Xuesong (Committee member) / Civil, Environmental and Sustainable Engineering Programs (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps.
ContributorsMartino, Todd Jeffrey (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2010
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
Women have evolved in the engineering profession over the decades. However, there is still a lot more room for female presence in the industry as women currently make up about 12-15% of working engineers. Based on many studies and surveys, it is clear that female confidence in their own performance and a feeling of belonging in the industry has evolved for the better. The studies and surveys also show that women still lack a certain confidence to get their engineering degree and then to pursue a career in engineering once they receive their degree. Research shows that the main cause for this is due to the stereotype that engineering is a masculine profession. Men and women both have this mindset because it has become a societal norm that most people go along with and do not even realize it. Unfortunately, it is very hard to overcome and change a societal norm, therefore, something needs to be done in order to fix this mindset. (Crawford). Based on studies and research, there are many ways the stereotype is being combatted. Social media has become a huge component in advocating for female engineers. Men and women are helping to fight the status quo by supporting female engineers and lobbying against people who think women do not belong in the industry. Industry professionals are teaming up with schools to figure out ways to make STEM programs more exciting for all young kids, but especially girls. They are also working to provide more mentors and role models for young girls in order to cheer them on and make them more confident in their abilities when learning and applying the STEM curriculum, as studies have proven that providing young girls with mentors can really help foster more female engineers in the long run. (Crawford). With all of the positive support and promotions of female engineers in the past few years, it is evident that women can certainly progress at a much faster pace than in previous decades.
ContributorsAcosta, Jazlyn (Co-author) / Venne, Hunter (Co-author) / Ward, Kristen (Thesis director) / Lou, Yingyan (Committee member) / Civil, Environmental and Sustainable Engineering Programs (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
This project report contains the design of a low-cost structural model of a residential structure in the City of Phoenix, AZ. The structural unit will be part of a residential area in Ahwatukee Foothills Village located just south of South Mountain. The residential structure is 3600 square feet and consists of three bedrooms (including the master bedroom), two bathrooms (including the master bathroom), a 2-car garage, laundry room, kitchen, dining room, and a living room. There are two elevation options (A & B) for the roof framing plan. Elevation A includes a straight forward truss package consisting of two truss designs with no hip or girder trusses. Elevation B includes a more complex truss package which includes girder trusses, hip trusses, and corner jacks. Within both elevations, the trusses run perpendicular to the ridge of the structure as displayed in the Architectural Floor Plan (see Figure 4) with the exception of the hip trusses and corner jacks in Elevation B.
The design objective is to meet all safety specifications while minimizing the total cost of members and member connections. The design also aims to streamline the construction time and resources by using standard member cross section dimensions. This residential building report is carried out in accordance with the City of Phoenix standards and follows the ASCE7-10 code for the dead and live load combinations and wind pressures. This report also references the National Design Specifications (NDS) 2005 for the column design. HT Consulting Group is excited to create a safe and sustainable development for the residents within Ahwatukee Foothills Village.
The design objective is to meet all safety specifications while minimizing the total cost of members and member connections. The design also aims to streamline the construction time and resources by using standard member cross section dimensions. This residential building report is carried out in accordance with the City of Phoenix standards and follows the ASCE7-10 code for the dead and live load combinations and wind pressures. This report also references the National Design Specifications (NDS) 2005 for the column design. HT Consulting Group is excited to create a safe and sustainable development for the residents within Ahwatukee Foothills Village.
ContributorsHerrera-Theut, Joseph James (Author) / Ward, Kristen (Thesis director) / Morgan, John (Committee member) / Civil, Environmental and Sustainable Eng Program (Contributor) / Barrett, The Honors College (Contributor)
Created2019-05
Description
There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.
ContributorsHabibiMehr, Payam (Author) / Thornton, Trevor John (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Formicone, Gabriele (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2019