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Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.
ContributorsHabibiMehr, Payam (Author) / Thornton, Trevor John (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Formicone, Gabriele (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2019
Description
The field of robotics is rapidly expanding, and with it, the methods of teaching and introducing students must also advance alongside new technologies. There is a challenge in robotics education, especially at high school levels, to expose them to more modern and practical robots. One way to bridge this gap is human-robot interaction for a more hands-on and impactful experience that will leave students more interested in pursuing the field. Our project is a Robotic Head Kit that can be used in an educational setting to teach about its electrical, mechanical, programming, and psychological concepts. We took an existing robot head prototype and further advanced it so it can be easily assembled while still maintaining human complexity. Our research for this project dove into the electronics, mechanics, software, and even psychological barriers present in order to advance the already existing head design. The kit we have developed combines the field of robotics with psychology to create and add more life-like features and functionality to the robot, nicknamed "James Junior." The goal of our Honors Thesis was to initially fix electrical, mechanical, and software problems present. We were then tasked to run tests with high school students to validate our assembly instructions while gathering their observations and feedback about the robot's programmed reactions and emotions. The electrical problems were solved with custom PCBs designed to power and program the existing servo motors on the head. A new set of assembly instructions were written and modifications to the 3D printed parts were made for the kit. In software, existing code was improved to implement a user interface via keypad and joystick to give students control of the robot head they construct themselves. The results of our tests showed that we were not only successful in creating an intuitive robot head kit that could be easily assembled by high school students, but we were also successful in programming human-like expressions that could be emotionally perceived by the students.
ContributorsRathke, Benjamin (Co-author) / Rivera, Gerardo (Co-author) / Sodemann, Angela (Thesis director) / Itagi, Manjunath (Committee member) / Engineering Programs (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
The Phoenix CubeSat is a 3U Earth imaging CubeSat which will take infrared (IR) photos of cities in the United Stated to study the Urban Heat Island Effect, (UHI) from low earth orbit (LEO). It has many different components that need to be powered during the life of its mission. The only power source during the mission will be its solar panels. It is difficult to calculate power generation from solar panels by hand because of the different orientations the satellite will be positioned in during orbit; therefore, simulation will be used to produce power generation data. Knowing how much power is generated is integral to balancing the power budget, confirming whether there is enough power for all the components, and knowing whether there will be enough power in the batteries during eclipse. This data will be used to create an optimal design for the Phoenix CubeSat to accomplish its mission.
ContributorsBarakat, Raymond John (Author) / White, Daniel (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2017-05
Description
Current technology does not allow for the full amount of power produced by solar arrays (PV) on spacecraft to be utilized. The arrays are designed with non-reconfigurable architectures and sent on fifteen to twenty year long missions. They cannot be changed once they are in space, so the arrays are designed for the end of life. Throughout their lifetime, solar arrays can degrade in power producing capabilities anywhere from 20% to 50%. Because there is such a drastic difference in the beginning and end of life power production, and because they cannot be reconfigured, a new design has been found necessary in order to increase power production. Reconfiguration allows the solar arrays to achieve maximum power producing capabilities at both the beginning and end of their lives. With the potential to increase power production by 50%, the reconfiguration design consists of a switching network to be able to utilize any combination of cells. The design for reconfiguration must meet the power requirements of the solar array. This thesis will explore different designs for reconfiguration, as well as possible switches for implementation. It will also review other methods to increase power production, as well as discuss future work in this field.
ContributorsJohnson, Everett Hope (Author) / Kitchen, Jennifer (Thesis director) / Ozev, Sule (Committee member) / School of International Letters and Cultures (Contributor) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
The action/adventure game Grad School: HGH is the final, extended version of a BME Prototyping class project in which the goal was to produce a zombie-themed game that teaches biomedical engineering concepts. The gameplay provides fast paced, exciting, and mildly addicting rooms that the player must battle and survive through, followed by an engineering puzzle that must be solved in order to advance to the next room. The objective of this project was to introduce the core concepts of BME to prospective students, rather than attempt to teach an entire BME curriculum. Based on user testing at various phases in the project, we concluded that the gameplay was engaging enough to keep most users' interest through the educational puzzles, and the potential for expanding this project to reach an even greater audience is vast.
ContributorsNitescu, George (Co-author) / Medawar, Alexandre (Co-author) / Spano, Mark (Thesis director) / LaBelle, Jeffrey (Committee member) / Guiang, Kristoffer (Committee member) / Barrett, The Honors College (Contributor) / Harrington Bioengineering Program (Contributor)
Created2014-05
Description
The field of soft robotics is a very quickly growing field that has yet to be fully explored or implemented in all of the possible applications. Soft robotics shows the greatest degree of possibility for mimicking biological systems effectively and accurately. This study seeks to set the groundwork for the development of a biomimetic nautilus using soft robotic methods. The study shows background research and discusses the methods used to develop a nautilus themed sub aquatic robot that uses a double bladder system and a pump to generate thrust for movement. The study shows how the unit would be fabricated and constructed. The study also explores why the second stage of the design failed and how it could potentially be fixed in future iterations.
ContributorsCarlson, Caleb Elijah (Author) / Polygerinos, Panagiotis (Thesis director) / Parsey, John (Committee member) / Engineering Programs (Contributor) / Barrett, The Honors College (Contributor)
Created2017-05
Description
The goal of our research was to develop and validate a method for predicting the mechanical behavior of Additively Manufactured multi-material honeycomb structures. Multiple approaches already exist in the field for modeling the behavior of cellular materials, including the bulk property assumption, homogenization and strut level characterization [1]. With the bulk property approach, the structure is assumed to behave according to what is known about the material in its bulk formulation, without regard to its geometry or scale. With the homogenization technique, the specimen that is being tested is treated as a solid material within the simulation environment even if the physical specimen is not. Then, reduced mechanical properties are assigned to the specimen to account for any voids that exist within the physical specimen. This approach to mechanical behavior prediction in cellular materials is shape dependent. In other words, the same model cannot be used from one specimen to the next if the cell shapes of those lattices differ in any way. When using the strut level characterization approach, a single strut (the connecting member between nodes constituting a cellular material) is isolated and tested. With this approach, there tends to be a significant deviation in the experimental data due to the small size of the isolated struts. Yet it has the advantage of not being shape sensitive, at least in principle. The method that we developed, and chose to test lies within the latter category, and is what we have coined as the Representative Lattice Element (RLE) Method. This method is modeled after the well-established Representative Volume Element (RVE) method [2]. We define the RLE as the smallest unit over which mechanical tests can be conducted that will provide results which are representative of the larger lattice structure. In other words, the theory is that a single member (or beam in this case) of a honeycomb structure can be taken, tests can be conducted on this member to determine the mechanical properties of the representative lattice element and the results will be representative of the mechanical behavior whole structure. To investigate this theory, we designed specimens, conducted various tensile and compression tests, analyzed the recorded data, conducted a micromechanics study, and performed structural simulation work using commercial Finite Element Analysis software.
ContributorsSalti, Ziyad Zuheir (Co-author) / Eppley, Trevor (Co-author) / Bhate, Dhruv (Thesis director) / Song, Kenan (Committee member) / Engineering Programs (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
ContributorsBakliwal, Priyanka (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
Description
Since the inception of Internet of Things (IoT) framework, the amount of interaction between electronic devices has tremendously increased and the ease of implementing software between such devices has bettered. Such data exchange between devices, whether between Node to Server or Node to Node, has paved way for creating new business models. Wireless Video Sensor Network Platforms are being used to monitor and understand the surroundings better. Both hardware and software supporting such devices have become much smaller and yet stronger to enable these. Specifically, the invention of better software that enable Wireless data transfer have become more simpler and lightweight technologies such as HTML5 for video rendering, Common Gateway Interface(CGI) scripts enabling interactions between client and server and WebRTC from Google for peer to peer interactions. The role of web browsers in enabling these has been vastly increasing.
Although HTTP is the most reliable and consistent data transfer protocol for such interactions, the most important underlying challenge with such platforms is the performance based on power consumption and latency in data transfer.
In the scope of this thesis, two applications using CGI and WebRTC for data transfer over HTTP will be presented and the power consumption by the peripherals in transmitting the data and the possible implications for those will be discussed.
Although HTTP is the most reliable and consistent data transfer protocol for such interactions, the most important underlying challenge with such platforms is the performance based on power consumption and latency in data transfer.
In the scope of this thesis, two applications using CGI and WebRTC for data transfer over HTTP will be presented and the power consumption by the peripherals in transmitting the data and the possible implications for those will be discussed.
ContributorsRentala, Sri Harsha (Author) / Reisslein, Martin (Thesis advisor) / Kitchen, Jennifer (Committee member) / McGarry, Michael (Committee member) / Arizona State University (Publisher)
Created2016