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- All Subjects: engineering
- Creators: Phelan, Patrick
- Creators: Bakkaloglu, Bertan
Description
ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed.
ContributorsKumar, Sushil (Author) / Clark, Lawrence (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
An eco-industrial park (EIP) is an industrial ecosystem in which a group of co-located firms are involved in collective resource optimization with each other and with the local community through physical exchanges of energy, water, materials, byproducts and services - referenced in the industrial ecology literature as "industrial symbiosis". EIPs, when compared with standard industrial resource sharing networks, prove to be of greater public advantage as they offer improved environmental and economic benefits, and higher operational efficiencies both upstream and downstream in their supply chain.
Although there have been many attempts to adapt EIP methodology to existing industrial sharing networks, most of them have failed for various factors: geographic restrictions by governmental organizations on use of technology, cost of technology, the inability of industries to effectively communicate their upstream and downstream resource usage, and to diminishing natural resources such as water, land and non-renewable energy (NRE) sources for energy production.
This paper presents a feasibility study conducted to evaluate the comparative environmental, economic, and geographic impacts arising from the use of renewable energy (RE) and NRE to power EIPs. Life Cycle Assessment (LCA) methodology, which is used in a variety of sectors to evaluate the environmental merits and demerits of different kinds of products and processes, was employed for comparison between these two energy production methods based on factors such as greenhouse gas emission, acidification potential, eutrophication potential, human toxicity potential, fresh water usage and land usage. To complement the environmental LCA analysis, levelized cost of electricity was used to evaluate the economic impact. This model was analyzed for two different geographic locations; United States and Europe, for 12 different energy production technologies.
The outcome of this study points out the environmental, economic and geographic superiority of one energy source over the other, including the total carbon dioxide equivalent emissions, which can then be related to the total number of carbon credits that can be earned or used to mitigate the overall carbon emission and move closer towards a net zero carbon footprint goal thus making the EIPs truly sustainable.
Although there have been many attempts to adapt EIP methodology to existing industrial sharing networks, most of them have failed for various factors: geographic restrictions by governmental organizations on use of technology, cost of technology, the inability of industries to effectively communicate their upstream and downstream resource usage, and to diminishing natural resources such as water, land and non-renewable energy (NRE) sources for energy production.
This paper presents a feasibility study conducted to evaluate the comparative environmental, economic, and geographic impacts arising from the use of renewable energy (RE) and NRE to power EIPs. Life Cycle Assessment (LCA) methodology, which is used in a variety of sectors to evaluate the environmental merits and demerits of different kinds of products and processes, was employed for comparison between these two energy production methods based on factors such as greenhouse gas emission, acidification potential, eutrophication potential, human toxicity potential, fresh water usage and land usage. To complement the environmental LCA analysis, levelized cost of electricity was used to evaluate the economic impact. This model was analyzed for two different geographic locations; United States and Europe, for 12 different energy production technologies.
The outcome of this study points out the environmental, economic and geographic superiority of one energy source over the other, including the total carbon dioxide equivalent emissions, which can then be related to the total number of carbon credits that can be earned or used to mitigate the overall carbon emission and move closer towards a net zero carbon footprint goal thus making the EIPs truly sustainable.
ContributorsGupta, Vaibhav (Author) / Calhoun, Ronald J (Thesis advisor) / Dooley, Kevin (Committee member) / Phelan, Patrick (Committee member) / Arizona State University (Publisher)
Created2014
Description
As the demand for power increases in populated areas, so will the demand for water. Current power plant technology relies heavily on the Rankine cycle in coal, nuclear and solar thermal power systems which ultimately use condensers to cool the steam in the system. In dry climates, the amount of water to cool off the condenser can be extremely large. Current wet cooling technologies such as cooling towers lose water from evaporation. One alternative to prevent this would be to implement a radiative cooling system. More specifically, a system that utilizes the volumetric radiation emission from water to the night sky could be implemented. This thesis analyzes the validity of a radiative cooling system that uses direct radiant emission to cool water. A brief study on potential infrared transparent cover materials such as polyethylene (PE) and polyvinyl carbonate (PVC) was performed. Also, two different experiments to determine the cooling power from radiation were developed and run. The results showed a minimum cooling power of 33.7 W/m2 for a vacuum insulated glass system and 37.57 W/m2 for a tray system with a maximum of 98.61 Wm-2 at a point when conduction and convection heat fluxes were considered to be zero. The results also showed that PE proved to be the best cover material. The minimum numerical results compared well with other studies performed in the field using similar techniques and materials. The results show that a radiative cooling system for a power plant could be feasible given that the cover material selection is narrowed down, an ample amount of land is available and an economic analysis is performed proving it to be cost competitive with conventional systems.
ContributorsOvermann, William (Author) / Phelan, Patrick (Thesis advisor) / Trimble, Steve (Committee member) / Taylor, Robert (Committee member) / Arizona State University (Publisher)
Created2011
Description
In this thesis the performance of a Hybrid AC System (HACS) is modeled and optimized. The HACS utilizes solar photovoltaic (PV) panels to help reduce the demand from the utility during peak hours. The system also includes an ice Thermal Energy Storage (TES) tank to accumulate cooling energy during off-peak hours. The AC runs continuously on grid power during off-peak hours to generate cooling for the house and to store thermal energy in the TES. During peak hours, the AC runs on the power supplied from the PV, and cools the house along with the energy stored in the TES. A higher initial cost is expected due to the additional components of the HACS (PV and TES), but a lower operational cost due to higher energy efficiency, energy storage and renewable energy utilization. A house cooled by the HACS will require a smaller size AC unit (about 48% less in the rated capacity), compared to a conventional AC system. To compare the cost effectiveness of the HACS with a regular AC system, time-of-use (TOU) utility rates are considered, as well as the cost of the system components and the annual maintenance. The model shows that the HACS pays back its initial cost of $28k in about 6 years with an 8% APR, and saves about $45k in total cost when compared to a regular AC system that cools the same house for the same period of 6 years.
ContributorsJubran, Sadiq (Author) / Phelan, Patrick (Thesis advisor) / Calhoun, Ronald (Committee member) / Trimble, Steve (Committee member) / Arizona State University (Publisher)
Created2011
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
The ability to shift the photovoltaic (PV) power curve and make the energy accessible during peak hours can be accomplished through pairing solar PV with energy storage technologies. A prototype hybrid air conditioning system (HACS), built under supervision of project head Patrick Phelan, consists of PV modules running a DC compressor that operates a conventional HVAC system paired with a second evaporator submerged within a thermal storage tank. The thermal storage is a 0.284m3 or 75 gallon freezer filled with Cryogel balls, submerged in a weak glycol solution. It is paired with its own separate air handler, circulating the glycol solution. The refrigerant flow is controlled by solenoid valves that are electrically connected to a high and low temperature thermostat. During daylight hours, the PV modules run the DC compressor. The refrigerant flow is directed to the conventional HVAC air handler when cooling is needed. Once the desired room temperature is met, refrigerant flow is diverted to the thermal storage, storing excess PV power. During peak energy demand hours, the system uses only small amounts of grid power to pump the glycol solution through the air handler (note the compressor is off), allowing for money and energy savings. The conventional HVAC unit can be scaled down, since during times of large cooling demands the glycol air handler can be operated in parallel with the conventional HVAC unit. Four major test scenarios were drawn up in order to fully comprehend the performance characteristics of the HACS. Upon initial running of the system, ice was produced and the thermal storage was charged. A simple test run consisting of discharging the thermal storage, initially ~¼ frozen, was performed. The glycol air handler ran for 6 hours and the initial cooling power was 4.5 kW. This initial test was significant, since greater than 3.5 kW of cooling power was produced for 3 hours, thus demonstrating the concept of energy storage and recovery.
ContributorsPeyton-Levine, Tobin (Author) / Phelan, Patrick (Thesis advisor) / Trimble, Steve (Committee member) / Wang, Robert (Committee member) / Arizona State University (Publisher)
Created2012
Description
Biosensors aiming at detection of target analytes, such as proteins, microbes, virus, and toxins, are widely needed for various applications including detection of chemical and biological warfare (CBW) agents, biomedicine, environmental monitoring, and drug screening. Surface Plasmon Resonance (SPR), as a surface-sensitive analytical tool, can very sensitively respond to minute changes of refractive index occurring adjacent to a metal film, offering detection limits up to a few ppt (pg/mL). Through SPR, the process of protein adsorption may be monitored in real-time, and transduced into an SPR angle shift. This unique technique bypasses the time-consuming, labor-intensive labeling processes, such as radioisotope and fluorescence labeling. More importantly, the method avoids the modification of the biomarker’s characteristics and behaviors by labeling that often occurs in traditional biosensors. While many transducers, including SPR, offer high sensitivity, selectivity is determined by the bio-receptors. In traditional biosensors, the selectivity is provided by bio-receptors possessing highly specific binding affinity to capture target analytes, yet their use in biosensors are often limited by their relatively-weak binding affinity with analyte, non-specific adsorption, need for optimization conditions, low reproducibility, and difficulties integrating onto the surface of transducers. In order to circumvent the use of bio-receptors, the competitive adsorption of proteins, termed the Vroman effect, is utilized in this work. The Vroman effect was first reported by Vroman and Adams in 1969. The competitive adsorption targeted here occurs among different proteins competing to adsorb to a surface, when more than one type of protein is present. When lower-affinity proteins are adsorbed on the surface first, they can be displaced by higher-affinity proteins arriving at the surface at a later point in time. Moreover, only low-affinity proteins can be displaced by high-affinity proteins, typically possessing higher molecular weight, yet the reverse sequence does not occur. The SPR biosensor based on competitive adsorption is successfully demonstrated to detect fibrinogen and thyroglobulin (Tg) in undiluted human serum and copper ions in drinking water through the denatured albumin.
ContributorsWang, Ran (Author) / Chae, Junseok (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tsow, Tsing (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2015
Description
Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
ContributorsHegde, Ashwath (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2018
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018