Matching Items (2)
Filtering by
- All Subjects: engineering
- Member of: Theses and Dissertations
- Status: Published
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
Modern radio frequency (RF) sensors are digital systems characterized by wide band frequency range, and capable to perform multi-function tasks such as: radar, electronic warfare (EW), and communications simultaneously on different sub-arrays. This demands careful understanding of the behavior of each sub-system and how each sub-array interacts with the others. A way to estimate and measure the active reflection coefficient (ARC) to calculate the active voltage standing wave ratio (VSWR) of multiple input multiple output (MIMO) radar when elements (or sub-arrays) are driven with different waveforms has been developed. This technique will help to understand and incorporate bounds in the design of MIMO systems and its waveforms to avoid damages by large power reflections and to improve system performance. The methodology developed consists of evaluating the active VSWR at each individual antenna element or sub-array from (1) estimates of the ARC by using computational electromagnetic (CEM) tools or (2) by directly measuring the ARC at each antenna element or sub-array. The former methodology is important especially at the design phase where trade offs between element shapes and geometrical configurations are taking place. The former methodology is expanded by directly measuring ARC using an experimental radar testbed Baseband-digital at Every Element MIMO Experimental Radar (BEEMER) system to assess the active VSWR, side-lobe levels and antenna pattern effects when different waveforms are transmitted. An optimization technique is implemented to mitigate the effects of the ARC in co-located MIMO radars by waveform design.
ContributorsColonDiaz, Nivia (Author) / Aberle, James T. (Thesis advisor) / Bliss, Daniel W. (Thesis advisor) / Diaz, Rodolfo (Committee member) / Janning, Dan (Committee member) / Arizona State University (Publisher)
Created2021