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- All Subjects: engineering
- Creators: Bakkaloglu, Bertan
- Creators: Ayyanar, Raja
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
The high penetration of photovoltaic (PV) both at the utility and at the distribu-tion levels, has raised concerns about the reliability of grid-tied inverters of PV power systems. Inverters are generally considered as the weak link in PV power systems. The lack of a dedicated qualification/reliability standard for PV inverters is a main barrier in realizing higher level of confidence in reliability. Development of a well-accepted design qualification standard specifically for PV inverters will help pave the way for significant improvement in reliability and performance of inverters across the entire industry. The existing standards for PV inverters such as UL 1741 and IEC 62109-1 primarily focus on safety. IEC 62093 discusses inverter qualification but it includes all the balance of sys-tem components and therefore not specific to PV inverters. There are other general stan-dards for distributed generators including the IEEE1547 series of standards which cover major concerns like utility integration but they are not dedicated to PV inverters and are not written from a design qualification point of view. In this thesis, some of the potential requirements for a design qualification standard for PV inverters are addressed. The IEC 62093 is considered as a guideline and the possible inclusions in the framework for a dedicated design qualification standard of PV inverter are discussed. The missing links in existing PV inverter related standards are identified by performing gap analysis. Dif-ferent requirements of small residential inverters compared to large utility-scale systems, and the emerging requirements on grid support features are also considered. Electric stress test is found to be the key missing link and one of the electric stress tests, the surge withstand test is studied in detail. The use of the existing standards for surge withstand test of residential scale PV inverters is investigated and a method to suitably adopt these standards is proposed. The proposed method is studied analytically and verified using simulation. A design criterion for choosing the switch ratings of the inverter that can per-form reliably under the surge environment is derived.
ContributorsAlampoondi Venkataramanan, Sai Balasubramanian (Author) / Ayyanar, Raja (Thesis advisor) / Vittal, Vijay (Committee member) / Heydt, Gerald (Committee member) / Arizona State University (Publisher)
Created2011
Description
In modern electric power systems, energy management systems (EMSs) are responsi-ble for monitoring and controlling the generation system and transmission networks. State estimation (SE) is a critical `must run successful' component within the EMS software. This is dictated by the high reliability requirements and need to represent the closest real time model for market operations and other critical analysis functions in the EMS. Tradi-tionally, SE is run with data obtained only from supervisory control and data acquisition (SCADA) devices and systems. However, more emphasis on improving the performance of SE drives the inclusion of phasor measurement units (PMUs) into SE input data. PMU measurements are claimed to be more accurate than conventional measurements and PMUs `time stamp' measurements accurately. These widely distributed devices meas-ure the voltage phasors directly. That is, phase information for measured voltages and currents are available. PMUs provide data time stamps to synchronize measurements. Con-sidering the relatively small number of PMUs installed in contemporary power systems in North America, performing SE with only phasor measurements is not feasible. Thus a hy-brid SE, including both SCADA and PMU measurements, is the reality for contemporary power system SE. The hybrid approach is the focus of a number of research papers. There are many practical challenges in incorporating PMUs into SE input data. The higher reporting rates of PMUs as compared with SCADA measurements is one of the salient problems. The disparity of reporting rates raises a question whether buffering the phasor measurements helps to give better estimates of the states. The research presented in this thesis addresses the design of data buffers for PMU data as used in SE applications in electric power systems. The system theoretic analysis is illustrated using an operating electric power system in the southwest part of the USA. Var-ious instances of state estimation data have been used for analysis purposes. The details of the research, results obtained and conclusions drawn are presented in this document.
ContributorsMurugesan, Veerakumar (Author) / Vittal, Vijay (Committee member) / Heydt, Gerald (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2013
Description
Solar power generation is the most promising technology to transfer energy consumption reliance from fossil fuel to renewable sources. Concentrated solar power generation is a method to concentrate the sunlight from a bigger area to a smaller area. The collected sunlight is converted more efficiently through two types of technologies: concentrated solar photovoltaics (CSPV) and concentrated solar thermal power (CSTP) generation. In this thesis, these two technologies were evaluated in terms of system construction, performance characteristics, design considerations, cost benefit analysis and their field experience. The two concentrated solar power generation systems were implemented with similar solar concentrators and solar tracking systems but with different energy collecting and conversion components: the CSPV system uses high efficiency multi-junction solar cell modules, while the CSTP system uses a boiler -turbine-generator setup. The performances are calibrated via the experiments and evaluation analysis.
ContributorsJin, Zhilei (Author) / Hui, Yu (Thesis advisor) / Ayyanar, Raja (Committee member) / Rodriguez, Armando (Committee member) / Arizona State University (Publisher)
Created2013
Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
The Smart Grid initiative describes the collaborative effort to modernize the U.S. electric power infrastructure. Modernization efforts incorporate digital data and information technology to effectuate control, enhance reliability, encourage small customer sited distributed generation (DG), and better utilize assets. The Smart Grid environment is envisioned to include distributed generation, flexible and controllable loads, bidirectional communications using smart meters and other technologies. Sensory technology may be utilized as a tool that enhances operation including operation of the distribution system. Addressing this point, a distribution system state estimation algorithm is developed in this thesis. The state estimation algorithm developed here utilizes distribution system modeling techniques to calculate a vector of state variables for a given set of measurements. Measurements include active and reactive power flows, voltage and current magnitudes, phasor voltages with magnitude and angle information. The state estimator is envisioned as a tool embedded in distribution substation computers as part of distribution management systems (DMS); the estimator acts as a supervisory layer for a number of applications including automation (DA), energy management, control and switching. The distribution system state estimator is developed in full three-phase detail, and the effect of mutual coupling and single-phase laterals and loads on the solution is calculated. The network model comprises a full three-phase admittance matrix and a subset of equations that relates measurements to system states. Network equations and variables are represented in rectangular form. Thus a linear calculation procedure may be employed. When initialized to the vector of measured quantities and approximated non-metered load values, the calculation procedure is non-iterative. This dissertation presents background information used to develop the state estimation algorithm, considerations for distribution system modeling, and the formulation of the state estimator. Estimator performance for various power system test beds is investigated. Sample applications of the estimator to Smart Grid systems are presented. Applications include monitoring, enabling demand response (DR), voltage unbalance mitigation, and enhancing voltage control. Illustrations of these applications are shown. Also, examples of enhanced reliability and restoration using a sensory based automation infrastructure are shown.
ContributorsHaughton, Daniel Andrew (Author) / Heydt, Gerald T (Thesis advisor) / Vittal, Vijay (Committee member) / Ayyanar, Raja (Committee member) / Hedman, Kory W (Committee member) / Arizona State University (Publisher)
Created2012
Description
ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps.
ContributorsMartino, Todd Jeffrey (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2010
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
The most important metrics considered for electric vehicles are power density, efficiency, and reliability of the powertrain modules. The powertrain comprises of an Electric Machine (EM), power electronic converters, an Energy Management System (EMS), and an Energy Storage System (ESS). The power electronic converters are used to couple the motor with the battery stack. Including a DC/DC converter in the powertrain module is favored as it adds an additional degree of freedom to achieve flexibility in optimizing the battery module and inverter independently. However, it is essential that the converter is rated for high peak power and can maintain high efficiency while operating over a wide range of load conditions to not compromise on system efficiency. Additionally, the converter must strictly adhere to all automotive standards.
Currently, several hard-switching topologies have been employed such as conventional boost DC/DC, interleaved step-up DC/DC, and full-bridge DC/DC converter. These converters face respective limitations in achieving high step-up conversion ratio, size and weight issues, or high component count. In this work, a bi-directional synchronous boost DC/DC converter with easy interleaving capability is proposed with a novel ZVT mechanism. This converter steps up the EV battery voltage of 200V-300V to a wide range of variable output voltages ranging from 310V-800V. High power density and efficiency are achieved through high switching frequency of 250kHz for each phase with effective frequency doubling through interleaving. Also, use of wide bandgap high voltage SiC switches allows high efficiency operation even at high temperatures.
Comprehensive analysis, design details and extensive simulation results are presented. Incorporating ZVT branch with adaptive time delay results in converter efficiency close to 98%. Experimental results from a 2.5kW hardware prototype validate the performance of the proposed approach. A peak efficiency of 98.17% has been observed in hardware in the boost or motoring mode.
Currently, several hard-switching topologies have been employed such as conventional boost DC/DC, interleaved step-up DC/DC, and full-bridge DC/DC converter. These converters face respective limitations in achieving high step-up conversion ratio, size and weight issues, or high component count. In this work, a bi-directional synchronous boost DC/DC converter with easy interleaving capability is proposed with a novel ZVT mechanism. This converter steps up the EV battery voltage of 200V-300V to a wide range of variable output voltages ranging from 310V-800V. High power density and efficiency are achieved through high switching frequency of 250kHz for each phase with effective frequency doubling through interleaving. Also, use of wide bandgap high voltage SiC switches allows high efficiency operation even at high temperatures.
Comprehensive analysis, design details and extensive simulation results are presented. Incorporating ZVT branch with adaptive time delay results in converter efficiency close to 98%. Experimental results from a 2.5kW hardware prototype validate the performance of the proposed approach. A peak efficiency of 98.17% has been observed in hardware in the boost or motoring mode.
ContributorsMullangi Chenchu, Hemanth (Author) / Ayyanar, Raja (Thesis advisor) / Qin, Jiangchao (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2018