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- All Subjects: FPGA
Description
This project examines the science of electric field sensing and completes experiments, gathering data to support its utility for various applications. The basic system consists of a transmitter, receiver, and lock-in amplifier. The primary goal of the study was to determine if such a system could detect a human disturbance, due to the capacitance of a human body, and such a thesis was supported. Much different results were obtained when a person disturbed the electric field transmitted by the system than when other types of objects, such as chairs and electronic devices, were placed in the field. In fact, there was a distinct difference between persons of varied sizes as well. This thesis goes through the basic design of the system and the process of experimental design for determining the capabilities of such an electric field sensing system.
ContributorsBranham, Breana Michelle (Author) / Allee, David (Thesis director) / Papandreou-Suppappola, Antonia (Committee member) / Phillips, Stephen (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor) / School of International Letters and Cultures (Contributor)
Created2013-05
Description
In-Band Full-Duplex (IBFD) can maximize the spectral resources and enable new types of technology, but generates self-interference (SI) that must be mitigated to enable practical applications. Analog domain SI cancellation (SIC), usually implemented as a digitally controlled adaptive filter, is one technique that is necessary to mitigate the interference below the noise floor. To maximize the efficiency and performance of the adaptive filter this thesis studies how key design choices impact the performance so that device designers can make better tradeoff decisions. Additionally, algorithms are introduced to maximize the SIC that incorporate the hardware constraints. The provided simulations show up to 45dB SIC with 7 bits of precision at 100MHz bandwidth.
ContributorsMorgenstern, Carl Willis (Author) / Bliss, Daniel W (Thesis advisor) / Herschfelt, Andrew (Committee member) / Papandreou-Suppappola, Antonia (Committee member) / Rong, Yu (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2023
Description
Machine learning is a powerful tool for processing and understanding the vast amounts of data produced by sensors every day. Machine learning has found use in a wide variety of fields, from making medical predictions through correlations invisible to the human eye to classifying images in computer vision applications. A wide range of machine learning algorithms have been developed to attempt to solve these problems, each with different metrics in accuracy, throughput, and energy efficiency. However, even after they are trained, these algorithms require substantial computations to make a prediction. General-purpose CPUs are not well-optimized to this task, so other hardware solutions have developed over time, including the use of a GPU, FPGA, or ASIC.
This project considers the FPGA implementations of MLP and CNN feedforward. While FPGAs provide significant performance improvements, they come at a substantial financial cost. We explore the options of implementing these algorithms on a smaller budget. We successfully implement a multilayer perceptron that identifies handwritten digits from the MNIST dataset on a student-level DE10-Lite FPGA with a test accuracy of 91.99%. We also apply our trained network to external image data loaded through a webcam and a Raspberry Pi, but we observe lower test accuracy in these images. Later, we consider the requirements necessary to implement a more elaborate convolutional neural network on the same FPGA. The study deems the CNN implementation feasible in the criteria of memory requirements and basic architecture. We suggest the CNN implementation on the same FPGA to be worthy of further exploration.
This project considers the FPGA implementations of MLP and CNN feedforward. While FPGAs provide significant performance improvements, they come at a substantial financial cost. We explore the options of implementing these algorithms on a smaller budget. We successfully implement a multilayer perceptron that identifies handwritten digits from the MNIST dataset on a student-level DE10-Lite FPGA with a test accuracy of 91.99%. We also apply our trained network to external image data loaded through a webcam and a Raspberry Pi, but we observe lower test accuracy in these images. Later, we consider the requirements necessary to implement a more elaborate convolutional neural network on the same FPGA. The study deems the CNN implementation feasible in the criteria of memory requirements and basic architecture. We suggest the CNN implementation on the same FPGA to be worthy of further exploration.
ContributorsLythgoe, Zachary James (Author) / Allee, David (Thesis director) / Hartin, Olin (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2019-12
Description
Precise Position, Navigation, and Timing (PNT) is necessary for the functioning of many critical infrastructure sectors relied upon by millions every day. Specifically, precise timing is primarily provided through the Global Positioning System (GPS) and its system of satellites that each house multiple atomic clocks. Without precise timing, utilities such as the internet, the power grid, navigational systems, and financial systems would cease operation. Because oscillator devices experience frequency drift during operation, many systems rely on the precise time provided by GPS to maintain synchronization across the globe. However, GPS signals are particularly susceptible to disruption – both intentional and unintentional – due to their space-based, low-power, and unencrypted nature. It is for these reasons that there is a need to develop a system that can provide an accurate timing reference – one disciplined by a GPS signal – and can also maintain its nominal frequency in scenarios of intermittent GPS availability.
This project considers an accurate timing reference deployed via Field Programmable Gate Array (FPGA) and disciplined by a GPS module. The objective is to implement a timing reference on a DE10-Lite FPGA disciplined by the 1 Pulse-Per-Second (PPS) output of an MTK3333 GPS module. When a signal lock is achieved with GPS, the MTK3333 delivers a pulse input to the FPGA on the leading edge of every second. The FPGA aligns a digital oscillator to this PPS reference, providing a disciplined output signal at a 10 MHz frequency that is maintained in events of intermittent GPS availability. The developed solution is evaluated using a frequency counter disciplined by an atomic clock in addition to an oscilloscope. The findings deem the software solution acceptable with more work needed to debug the hardware solution
ContributorsWitthus, Alexander (Author) / Allee, David (Thesis director) / Hartin, Olin (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2022-05