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- All Subjects: Materials Science
- All Subjects: engineering
- Creators: Jiao, Yang
- Creators: Goryll, Michael
Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Carrier lifetime is one of the few parameters which can give information about the low defect densities in today's semiconductors. In principle there is no lower limit to the defect density determined by lifetime measurements. No other technique can easily detect defect densities as low as 10-9 - 10-10 cm-3 in a simple, contactless room temperature measurement. However in practice, recombination lifetime τr measurements such as photoconductance decay (PCD) and surface photovoltage (SPV) that are widely used for characterization of bulk wafers face serious limitations when applied to thin epitaxial layers, where the layer thickness is smaller than the minority carrier diffusion length Ln. Other methods such as microwave photoconductance decay (µ-PCD), photoluminescence (PL), and frequency-dependent SPV, where the generated excess carriers are confined to the epitaxial layer width by using short excitation wavelengths, require complicated configuration and extensive surface passivation processes that make them time-consuming and not suitable for process screening purposes. Generation lifetime τg, typically measured with pulsed MOS capacitors (MOS-C) as test structures, has been shown to be an eminently suitable technique for characterization of thin epitaxial layers. It is for these reasons that the IC community, largely concerned with unipolar MOS devices, uses lifetime measurements as a "process cleanliness monitor." However when dealing with ultraclean epitaxial wafers, the classic MOS-C technique measures an effective generation lifetime τg eff which is dominated by the surface generation and hence cannot be used for screening impurity densities. I have developed a modified pulsed MOS technique for measuring generation lifetime in ultraclean thin p/p+ epitaxial layers which can be used to detect metallic impurities with densities as low as 10-10 cm-3. The widely used classic version has been shown to be unable to effectively detect such low impurity densities due to the domination of surface generation; whereas, the modified version can be used suitably as a metallic impurity density monitoring tool for such cases.
ContributorsElhami Khorasani, Arash (Author) / Alford, Terry (Thesis advisor) / Goryll, Michael (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2013
Description
Photodetectors in the 1.7 to 4.0 μm range are being commercially developed on InP substrates to meet the needs of longer wavelength applications such as thermal and medical sensing. Currently, these devices utilize high indium content metamorphic Ga1-xInxAs (x > 0.53) layers to extend the wavelength range beyond the 1.7 μm achievable using lattice matched GaInAs. The large lattice mismatch required to reach the extended wavelengths results in photodetector materials that contain a large number of misfit dislocations. The low quality of these materials results in a large nonradiative Shockley Read Hall generation/recombination rate that is manifested as an undesirable large thermal noise level in these photodetectors. This work focuses on utilizing the different band structure engineering methods to design more efficient devices on InP substrates. One prospective way to improve photodetector performance at the extended wavelengths is to utilize lattice matched GaInAs/GaAsSb structures that have a type-II band alignment, where the ground state transition energy of the superlattice is smaller than the bandgap of either constituent material. Over the extended wavelength range of 2 to 3 μm this superlattice structure has an optimal period thickness of 3.4 to 5.2 nm and a wavefunction overlap of 0.8 to 0.4, respectively. In using a type-II superlattice to extend the cutoff wavelength there is a tradeoff between the wavelength reached and the electron-hole wavefunction overlap realized, and hence absorption coefficient achieved. This tradeoff and the subsequent reduction in performance can be overcome by two methods: adding bismuth to this type-II material system; applying strain on both layers in the system to attain strain-balanced condition. These allow the valance band alignment and hence the wavefunction overlap to be tuned independently of the wavelength cutoff. Adding 3% bismuth to the GaInAs constituent material, the resulting lattice matched Ga0.516In0.484As0.970Bi0.030/GaAs0.511Sb0.489superlattice realizes a 50% larger absorption coefficient. While as, similar results can be achieved with strain-balanced condition with strain limited to 1.9% on either layer. The optimal design rules derived from the different possibilities make it feasible to extract superlattice period thickness with the best absorption coefficient for any cutoff wavelength in the range.
ContributorsSharma, Ankur R (Author) / Johnson, Shane (Thesis advisor) / Goryll, Michael (Committee member) / Roedel, Ronald (Committee member) / Arizona State University (Publisher)
Created2013
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
With the progression of different industries moving away from employing secretaries for business professionals and professors, there exists a void in the area of personal assistance. This problem has existing solutions readily available to replace this service, i.e. secretary or personal assistant, tend to range from expensive and useful to inexpensive and not efficient. This leaves a low cost niche into the market of a virtual office assistant or manager to display messages and to help direct people in obtaining contact information. The development of a low cost solution revolves around the software needed to solve the various problems an accessible and user friendly Virtual Interface in which the owner of the Virtual Office Manager/Assistant can communicate to colleagues who are at standby outside of the owner's office and vice versa. This interface will be allowing the owner to describe the status pertaining to their absence or any other message sent to the interface. For example, the status of the owner's work commute can be described with a simple "Running Late" phrase or a message like "Busy come back in 10 minutes". In addition, any individual with an interest to these entries will have the opportunity to respond back because the device will provide contact information. When idle, the device will show supplemental information such as the owner's calendar and name. The scope of this will be the development and testing of solutions to achieve these goals.
ContributorsOffenberger, Spencer Eliot (Author) / Kozicki, Michael (Thesis director) / Goryll, Michael (Committee member) / Electrical Engineering Program (Contributor) / Computer Science and Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-12
Description
Widespread knowledge of fracture mechanics is mostly based on previous models that generalize crack growth in materials over several loading cycles. The objective of this project is to characterize crack growth that occurs in titanium alloys, specifically Grade 5 Ti-6Al-4V, at the sub-cycle scale, or within a single loading cycle. Using scanning electron microscopy (SEM), imaging analysis is performed to observe crack behavior at ten loading steps throughout the loading and unloading paths. Analysis involves measuring the incremental crack growth and crack tip opening displacement (CTOD) of specimens at loading ratios of 0.1, 0.3, and 0.5. This report defines the relationship between crack growth and the stress intensity factor, K, of the specimens, as well as the relationship between the R-ratio and stress opening level. The crack closure phenomena and effect of microcracks are discussed as they influence the crack growth behavior. This method has previously been used to characterize crack growth in Al 7075-T6. The results for Ti-6Al-4V are compared to these previous findings in order to strengthen conclusions about crack growth behavior.
ContributorsNazareno, Alyssa Noelle (Author) / Liu, Yongming (Thesis director) / Jiao, Yang (Committee member) / Mechanical and Aerospace Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
This research emphasizes the use of low energy and low temperature post processing to improve the performance and lifetime of thin films and thin film transistors, by applying the fundamentals of interaction of materials with conductive heating and electromagnetic radiation. Single frequency microwave anneal is used to rapidly recrystallize the damage induced during ion implantation in Si substrates. Volumetric heating of the sample in the presence of the microwave field facilitates quick absorption of radiation to promote recrystallization at the amorphous-crystalline interface, apart from electrical activation of the dopants due to relocation to the substitutional sites. Structural and electrical characterization confirm recrystallization of heavily implanted Si within 40 seconds anneal time with minimum dopant diffusion compared to rapid thermal annealed samples. The use of microwave anneal to improve performance of multilayer thin film devices, e.g. thin film transistors (TFTs) requires extensive study of interaction of individual layers with electromagnetic radiation. This issue has been addressed by developing detail understanding of thin films and interfaces in TFTs by studying reliability and failure mechanisms upon extensive stress test. Electrical and ambient stresses such as illumination, thermal, and mechanical stresses are inflicted on the mixed oxide based thin film transistors, which are explored due to high mobilities of the mixed oxide (indium zinc oxide, indium gallium zinc oxide) channel layer material. Semiconductor parameter analyzer is employed to extract transfer characteristics, useful to derive mobility, subthreshold, and threshold voltage parameters of the transistors. Low temperature post processing anneals compatible with polymer substrates are performed in several ambients (oxygen, forming gas and vacuum) at 150 °C as a preliminary step. The analysis of the results pre and post low temperature anneals using device physics fundamentals assists in categorizing defects leading to failure/degradation as: oxygen vacancies, thermally activated defects within the bandgap, channel-dielectric interface defects, and acceptor-like or donor-like trap states. Microwave anneal has been confirmed to enhance the quality of thin films, however future work entails extending the use of electromagnetic radiation in controlled ambient to facilitate quick post fabrication anneal to improve the functionality and lifetime of these low temperature fabricated TFTs.
ContributorsVemuri, Rajitha (Author) / Alford, Terry L. (Thesis advisor) / Theodore, N David (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Electromigration, the net atomic diffusion associated with the momentum transfer from electrons moving through a material, is a major cause of device and component failure in microelectronics. The deleterious effects from electromigration rise with increased current density, a parameter that will only continue to increase as our electronic devices get smaller and more compact. Understanding the dynamic diffusional pathways and mechanisms of these electromigration-induced and propagated defects can further our attempts at mitigating these failure modes. This dissertation provides insight into the relationships between these defects and parameters of electric field strength, grain boundary misorientation, grain size, void size, eigenstrain, varied atomic mobilities, and microstructure.First, an existing phase-field model was modified to investigate the various defect modes associated with electromigration in an equiaxed non-columnar microstructure. Of specific interest was the effect of grain boundary misalignment with respect to current flow and the mechanisms responsible for the changes in defect kinetics. Grain size, magnitude of externally applied electric field, and the utilization of locally distinct atomic mobilities were other parameters investigated. Networks of randomly distributed grains, a common microstructure of interconnects, were simulated in both 2- and 3-dimensions displaying the effects of 3-D capillarity on diffusional dynamics.
Also, a numerical model was developed to study the effect of electromigration on void migration and coalescence. Void migration rates were found to be slowed from compressive forces and the nature of the deformation concurrent with migration was examined through the lens of chemical potential. Void migration was also validated with previously reported theoretical explanations. Void coalescence and void budding were investigated and found to be dependent on the magnitude of interfacial energy and electric field strength.
A grasp on the mechanistic pathways of electromigration-induced defect evolution is imperative to the development of reliable electronics, especially as electronic devices continue to miniaturize. This dissertation displays a working understanding of the mechanistic pathways interconnects can fail due to electromigration, as well as provide direction for future research and understanding.
ContributorsFarmer, William McHann (Author) / Ankit, Kumar (Thesis advisor) / Chawla, Nikhilesh (Committee member) / Jiao, Yang (Committee member) / McCue, Ian (Committee member) / Arizona State University (Publisher)
Created2022
Description
Applications such as heat exchangers, surface-based cellular structures, rotating blades, and waveguides rely on thin metal walls as crucial constituent elements of the structure. The design freedom enabled by laser powder bed fusion has led to an interest in exploiting this technology to further the performance of these components, many of which retain their as-built surface morphologies on account of their design complexity. However, there is limited understanding of how and why mechanical properties vary by wall thickness for specimens that are additively manufactured and maintain an as-printed surface finish. Critically, the contributions of microstructure and morphology to the mechanical behavior of thin wall laser powder bed fusion structures have yet to be systematically identified and decoupled. This work focuses on elucidating the room temperature quasi-static tensile and high cycle fatigue properties of as-printed, thin-wall Inconel 718 fabricated using laser powder bed fusion, with the aim of addressing this critical gap in the literature. Wall thicknesses studied range from 0.3 - 2.0 mm, and the effects of Hot Isostatic Pressing are also examined, with sheet metal specimens used as a baseline for comparison. Statistical analyses are conducted to identify the significance of the dependence of properties on wall thickness and Hot Isostatic Pressing, as well as to examine correlations of these properties to section area, porosity, and surface roughness. A thorough microstructural study is complemented with a first-of-its-kind study of surface morphology to decouple their contributions and identify underlying causes for observed changes in mechanical properties. This thesis finds that mechanical properties in the quasi-static and fatigue framework do not see appreciable declines until specimen thickness is under 0.75 mm in thickness. The added Hot Isostatic Pressing heat treatment effectively closed pores, recrystallized the grain structure, and provided a more homogenous microstructure that benefits the modulus, tensile strength, elongation, and fatigue performance at higher stresses. Stress heterogeneities, primarily caused by surface defects, negatively affected the thinner specimens disproportionately. Without the use of the Hot Isostatic Pressing, the grain structure remained much more refined and benefitted the yield strength and fatigue endurance limit.
ContributorsParadise, Paul David (Author) / Bhate, Dhruv (Thesis advisor) / Chawla, Nikhilesh (Committee member) / Azeredo, Bruno (Committee member) / Jiao, Yang (Committee member) / Arizona State University (Publisher)
Created2022
Description
Microstructure refinement and alloy additions are considered potential routes to increase high temperature performance of existing metallic superalloys used under extreme conditions. Nanocrystalline (NC) Cu-10at%Ta exhibits such improvements over microstructurally unstable NC metals, leading to enhanced creep behavior compared to its coarse-grained (CG) counterparts. However, the low melting point of Cu compared to other FCC metals, e.g., Ni, might lead to an early onset of diffusional creep mechanisms. Thus, this research seeks to study the thermo-mechanical behavior and stability of hierarchical (prepared using arc-melting) and NC (prepared by collaborators through powder pressing and annealing) Ni-Y-Zr alloys where Zr is expected to provide solid solution and grain boundary strengthening in hierarchical and NC alloys, respectively, while Ni-Y and Ni-Zr intermetallic precipitates (IMCs) would provide kinetic stability. Hierarchical alloys had microstructures stable up to 1100 °C with ultrafine eutectic of ~300 nm, dendritic arm spacing of ~10 μm, and grain size ~1-2 mm. Room temperature hardness tests along with uniaxial compression performed at 25 and 600 °C revealed that microhardness and yield strength of hierarchical alloys with small amounts of Y (0.5-1wt%) and Zr (1.5-3 wt%) were comparable to Ni-superalloys, due to the hierarchical microstructure and potential presence of nanoscale IMCs. In contrast, NC alloys of the same composition were found to be twice as hard as the hierarchical alloys. Creep tests at 0.5 homologous temperature showed active Coble creep mechanisms in hierarchical alloys at low stresses with creep rates slower than Fe-based superalloys and dislocation creep mechanisms at higher stresses. Creep in NC alloys at lower stresses was only 20 times faster than hierarchical alloys, with the difference in grain size ranging from 10^3 to 10^6 times at the same temperature. These NC alloys showed enhanced creep properties over other NC metals and are expected to have rates equal to or improved over the CG hierarchical alloys with ECAP processing techniques. Lastly, the in-situ wide-angle x-ray scattering (WAXS) measurements during quasi-static and creep tests implied stresses being carried mostly by the matrix before yielding and in the primary creep stage, respectively, while relaxation was observed in Ni5Zr for both hierarchical and NC alloys. Beyond yielding and in the secondary creep stage, lattice strains reached a steady state, thereby, an equilibrium between plastic strain rates was achieved across different phases, so that deformation reaches a saturation state where strain hardening effects are compensated by recovery mechanisms.
ContributorsSharma, Shruti (Author) / Peralta, Pedro (Thesis advisor) / Alford, Terry (Committee member) / Jiao, Yang (Committee member) / Solanki, Kiran (Committee member) / Arizona State University (Publisher)
Created2022