Matching Items (20)
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- All Subjects: engineering
- All Subjects: RF
- Creators: Bakkaloglu, Bertan
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
With increasing demand for System on Chip (SoC) and System in Package (SiP) design in computer and communication technologies, integrated inductor which is an essential passive component has been widely used in numerous integrated circuits (ICs) such as in voltage regulators and RF circuits. In this work, soft ferromagnetic core material, amorphous Co-Zr-Ta-B, was incorporated into on-chip and in-package inductors in order to scale down inductors and improve inductors performance in both inductance density and quality factor. With two layers of 500 nm Co-Zr-Ta-B films a 3.5X increase in inductance and a 3.9X increase in quality factor over inductors without magnetic films were measured at frequencies as high as 1 GHz. By laminating technology, up to 9.1X increase in inductance and more than 5X increase in quality factor (Q) were obtained from stripline inductors incorporated with 50 nm by 10 laminated films with a peak Q at 300 MHz. It was also demonstrated that this peak Q can be pushed towards high frequency as far as 1GHz by a combination of patterning magnetic films into fine bars and laminations. The role of magnetic vias in magnetic flux and eddy current control was investigated by both simulation and experiment using different patterning techniques and by altering the magnetic via width. Finger-shaped magnetic vias were designed and integrated into on-chip RF inductors improving the frequency of peak quality factor from 400 MHz to 800 MHz without sacrificing inductance enhancement. Eddy current and magnetic flux density in different areas of magnetic vias were analyzed by HFSS 3D EM simulation. With optimized magnetic vias, high frequency response of up to 2 GHz was achieved. Furthermore, the effect of applied magnetic field on on-chip inductors was investigated for high power applications. It was observed that as applied magnetic field along the hard axis (HA) increases, inductance maintains similar value initially at low fields, but decreases at larger fields until the magnetic films become saturated. The high frequency quality factor showed an opposite trend which is correlated to the reduction of ferromagnetic resonant absorption in the magnetic film. In addition, experiments showed that this field-dependent inductance change varied with different patterned magnetic film structures, including bars/slots and fingers structures. Magnetic properties of Co-Zr-Ta-B films on standard organic package substrates including ABF and polyimide were also characterized. Effects of substrate roughness and stress were analyzed and simulated which provide strategies for integrating Co-Zr-Ta-B into package inductors and improving inductors performance. Stripline and spiral inductors with Co-Zr-Ta-B films were fabricated on both ABF and polyimide substrates. Maximum 90% inductance increase in hundreds MHz frequency range were achieved in stripline inductors which are suitable for power delivery applications. Spiral inductors with Co-Zr-Ta-B films showed 18% inductance increase with quality factor of 4 at frequency up to 3 GHz.
ContributorsWu, Hao (Author) / Yu, Hongbin (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Chickamenahalli, Shamala (Committee member) / Arizona State University (Publisher)
Created2013
Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps.
ContributorsMartino, Todd Jeffrey (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2010
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
The world has seen a revolution in cellular communication with the advent of 5G, which enables gigabits per second data speed with low latency, massive capacity, and increased availability. Complex modulated signals are used in these moderncommunication systems to achieve high spectral efficiency, and these signals exhibit high peak to average power ratios (PAPR). Design of cellular infrastructure hardware to support these complex signals therefore becomes challenging, as the transmitter’s radio frequency power amplifier (RF PA) needs to remain highly efficient at both peak and backed off power conditions. Additionally, these PAs should exhibit high linearity and support continually increasing bandwidths. Many advanced PA configurations exhibit high efficiency for processing legacy communications signals. Some of the most popular architectures are Envelope Elimination and Restoration (EER), Envelope Tracking (ET), Linear Amplification using Non-linear Component (LINC), Doherty Power Amplifiers (DPA), and Polar Transmitters. Among these techniques,
the DPA is the most widely used architecture for base-station applications because of its simple configuration and ability to be linearized using simple digital pre-distortion (DPD) algorithms. To support the cellular infrastructure needs of 5G and beyond, RF PAs, specifically DPA architectures, must be further enhanced to support broader bandwidths as well as smaller form-factors with higher levels of integration. The following four novel works are presented in this dissertation to support RF PA requirements for future cellular infrastructure:
1. A mathematical analysis to analyze the effects of non-linear parasitic capacitance (Cds) on the operation of continuous class-F (CCF) mode power amplifiers and identify their optimum operating range for high power and efficiency.
2. A methodology to incorporate a class-J harmonic trapping network inside the PA package by considering the effect of non-linear Cds, thus reducing the DPA footprint while achieving high RF performance.
3. A novel method of synthesizing the DPA’s output combining network (OCN) to realize an integrated two-stage integrated LDMOS asymmetric DPA.
4. A novel extended back-off efficiency range DPA architecture that engineers the mutual interaction between combining load and peaking off-state impedance. The theory and architecture are verified through a GaN-based DPA design.
ContributorsAhmed, Maruf Newaz (Author) / Kitchen, Jennifer (Thesis advisor) / Aberle, James (Committee member) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2022
Description
The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world.
Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.
Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.
ContributorsRuhul Hasin, Muhammad (Author) / Kitchen, Jennifer (Thesis advisor) / Aberle, James T., 1961- (Committee member) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2018
Description
There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.
ContributorsHabibiMehr, Payam (Author) / Thornton, Trevor John (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Formicone, Gabriele (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2019
Description
This work implements three switched mode power amplifier topologies namely inverse class-D (CMCD), push-pull class-E and inverse push-pull class-E, in a GaN-on-Si process for medium power level (5-10W) femto/pico-cells base-station applications. The presented power amplifiers address practical implementation design constraints and explore the fundamental performance limitations of switched-mode power amplifiers for cellular band. The designs are analyzed and compared with respect to non-idealities like finite on-resistance, finite-Q of inductors, bond-wire effects, input signal duty cycle, and supply and component variations. These architectures are designed for non-constant envelope inputs in the form of digitally modulated signals such as RFPWM, which undergo duty cycle variation. After comparing the three topologies, this work concludes that the inverse push-pull class-E power amplifier shows lower efficiency degradation at reduced duty cycles. For GaN based discrete power amplifiers which have less drain capacitance compared to GaAs or CMOS and where the switch loss is dominated by wire-bonds, an inverse push-pull class-E gives highest output power at highest efficiency. Push-pull class-E can give efficiencies comparable to inverse push-pull class-E in presence of bondwires on tuning the Zero-Voltage Switching (ZVS) network components but at a lower output power. Current-Mode Class-D (CMCD) is affected most by the presence of bondwires and gives least output power and efficiency compared to other two topologies. For systems dominated by drain capacitance loss or which has no bondwires, the CMCD and push-pull class-E gives better output power than inverse push-pull class-E. However, CMCD is more suitable for high breakdown voltage process.
ContributorsShukla, Shishir Ramasare (Author) / Kitchen, Jennifer N (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Trichopoulos, Georgios (Committee member) / Arizona State University (Publisher)
Created2015