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Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness,

Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming. This thesis proposes an analytical model to predict variability in CMOS circuits that is quick and accurate. There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ/μ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of Vth variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing Vth variation.
ContributorsGummalla, Samatha (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented

Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
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Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices

ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Optical receivers have many different uses covering simple infrared receivers, high speed fiber optic communication and light based instrumentation. All of them have an optical receiver that converts photons to current followed by a transimpedance amplifier to convert the current to a useful voltage. Different systems create different requirements for

Optical receivers have many different uses covering simple infrared receivers, high speed fiber optic communication and light based instrumentation. All of them have an optical receiver that converts photons to current followed by a transimpedance amplifier to convert the current to a useful voltage. Different systems create different requirements for each receiver. High speed digital communication require high throughput with enough sensitivity to keep the bit error rate low. Instrumentation receivers have a lower bandwidth, but higher gain and sensitivity requirements. In this thesis an optical receiver for use in instrumentation in presented. It is an entirely monolithic design with the photodiodes on the same substrate as the CMOS circuitry. This allows for it to be built into a focal-plane array, but it places some restriction on the area. It is also designed for in-situ testing and must be able to cancel any low frequency noise caused by ambient light. The area restrictions prohibit the use of a DC blocking capacitor to reject the low frequency noise. In place a servo loop was wrapped around the system to reject any DC offset. A modified Cherry-Hooper architecture was used for the transimpedance amplifier. This provides the flexibility to create an amplifier with high gain and wide bandwidth that is independent of the input capacitance. The downside is the increased complexity of the design makes stability paramount to the design. Another drawback is the high noise associated with low input impedance that decouples the input capacitance from the bandwidth. This problem is compounded by the servo loop feed which leaves the output noise of some amplifiers directly referred to the input. An in depth analysis of each circuit block's noise contribution is presented.
ContributorsLaFevre, Kyle (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Vermeire, Bert (Committee member) / Arizona State University (Publisher)
Created2011
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Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change

The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
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Description
The front end of almost all ADCs consists of a Sample and Hold Circuit in order to make sure a constant analog value is digitized at the end of ADC. The design of Track and Hold Circuit (THA) mainly focuses on following parameters: Input frequency, Sampling frequency, dynamic Range, hold

The front end of almost all ADCs consists of a Sample and Hold Circuit in order to make sure a constant analog value is digitized at the end of ADC. The design of Track and Hold Circuit (THA) mainly focuses on following parameters: Input frequency, Sampling frequency, dynamic Range, hold pedestal, feed through error. This thesis will discuss the importance of these parameters of a THA to the ADCs and commonly used architectures of THA. A new architecture with SiGe HBT transistors in BiCMOS 130 nm technology is presented here. The proposed topology without complicated circuitry achieves high Spurious Free Dynamic Range(SFDR) and Total Harmonic Distortion (THD).These are important figure of merits for any THA which gives a measure of non-linearity of the circuit. The proposed topology is implemented in IBM8HP 130 nm BiCMOS process combines typical emitter follower switch in bipolar THAs and output steering technique proposed in the previous work. With these techniques and the cascode transistor in the input which is used to isolate the switch from the input during the hold mode, better results have been achieved. The THA is designed to work with maximum input frequency of 250 MHz at sampling frequency of 500 MHz with input currents not more than 5mA achieving an SFDR of 78.49 dB. Simulation and results are presented, illustrating the advantages and trade-offs of the proposed topology.
ContributorsRao, Nishita Ramakrishna (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
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Description
The non-quasi-static (NQS) description of device behavior is useful in fast switching and high frequency circuit applications. Hence, it is necessary to develop a fast and accurate compact NQS model for both large-signal and small-signal simulations. A new relaxation-time-approximation based NQS MOSFET model, consistent between transient and small-signal simulations, has

The non-quasi-static (NQS) description of device behavior is useful in fast switching and high frequency circuit applications. Hence, it is necessary to develop a fast and accurate compact NQS model for both large-signal and small-signal simulations. A new relaxation-time-approximation based NQS MOSFET model, consistent between transient and small-signal simulations, has been developed for surface-potential-based MOSFET compact models. The new model is valid for all regions of operation and is compatible with, and at low frequencies recovers, the quasi-static (QS) description of the MOSFET. The model is implemented in two widely used circuit simulators and tested for speed and convergence. It is verified by comparison with technology computer aided design (TCAD) simulations and experimental data, and by application of a recently developed benchmark test for NQS MOSFET models. In addition, a new and simple technique to characterize NQS and gate resistance, Rgate, MOS model parameters from measured data has been presented. In the process of experimental model verification, the effects of bulk resistance on MOSFET characteristics is investigated both theoretically and experimentally to separate it from the NQS effects.
ContributorsZhu, Zeqin (Author) / Gildenblat, Gennady (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Barnaby, Hugh (Committee member) / Mcandrew, Colin C (Committee member) / Arizona State University (Publisher)
Created2012
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Description

Pelvic Circumferential Compression Devices (PCCDs), an important medical device when caring for patients with pelvic fractures, play a crucial role in the stabilization and reduction of the fracture. During pelvic fracture cases, control of internal bleeding through access to the femoral artery is of utmost importance. Current designs of PCCDs

Pelvic Circumferential Compression Devices (PCCDs), an important medical device when caring for patients with pelvic fractures, play a crucial role in the stabilization and reduction of the fracture. During pelvic fracture cases, control of internal bleeding through access to the femoral artery is of utmost importance. Current designs of PCCDs do not allow vital access to this artery and in attempts to gain access, medical professionals and emergency care providers choose to cut into the PCCDs or place them in suboptimal positions with unknown downstream effects. We researched the effects on surface pressure and the overall pressure distribution created by the PCCDs when they are modified or placed incorrectly on the patient. In addition, we investigated the effects of those misuses on pelvic fracture reduction, a key parameter in stabilizing the patient during critical care. We hypothesized that incorrectly placing or modifying the PCCD will result in increased surface pressure and decreased fracture reduction. Our mannequin studies show that for SAM Sling and T-POD, surface pressure increases if a PCCD is incorrectly placed or modified, in support of our hypothesis. However, opposite results occurred for the Pelvic Binder, where the correctly placed PCCD had higher surface pressure when compared to the incorrectly placed or modified PCCD. Additionally, pressure distribution was significantly affected by the modification of the PCCDs. The cadaver lab measurements show that modifying or incorrectly placing the PCCDs significantly limits their ability to reduce the pelvic fracture. These results suggest that while modifying or incorrectly placing PCCDs allows access to the femoral artery, there are potentially dangerous effects to the patient including increased surface pressures and limited fracture reduction.

ContributorsConley, Ian Patrick (Co-author) / Ryder, Madison (Co-author) / Vernon, Brent (Thesis director) / Bogert, James (Committee member) / Harrington Bioengineering Program (Contributor) / School of Mathematical and Statistical Sciences (Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
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Description
To supplement lectures, various resources are available to students; however, little research has been done to look systematically at which resources studies find most useful and the frequency at which they are used. We have conducted a preliminary study looking at various resources available in an introductory material science course

To supplement lectures, various resources are available to students; however, little research has been done to look systematically at which resources studies find most useful and the frequency at which they are used. We have conducted a preliminary study looking at various resources available in an introductory material science course over four semesters using a custom survey called the Student Resource Value Survey (SRVS). More specifically, the SRVS was administered before each test to determine which resources students use to do well on exams. Additionally, over the course of the semester, which resources students used changed. For instance, study resources for exams including the use of homework problems decreased from 81% to 50%, the utilization of teaching assistant for exam studying increased from 25% to 80%, the use of in class Muddiest Points for exam study increased form 28% to 70%, old exams and quizzes only slightly increased for exam study ranging from 78% to 87%, and the use of drop-in tutoring services provided to students at no charge decreased from 25% to 17%. The data suggest that students thought highly of peer interactions by using those resources more than tutoring centers. To date, no research has been completed looking at courses at the department level or a different discipline. To this end, we adapted the SRVS administered in material science to investigate resource use in thirteen biomedical engineering (BME) courses. Here, we assess the following research question: "From a variety of resources, which do biomedical engineering students feel addresses difficult concept areas, prepares them for examinations, and helps in computer-aided design (CAD) and programming the most and with what frequency?" The resources considered include teaching assistants, classroom notes, prior exams, homework problems, Muddiest Points, office hours, tutoring centers, group study, and the course textbook. Results varied across the four topical areas: exam study, difficult concept areas, CAD software, and math-based programming. When preparing for exams and struggling with a learning concept, the most used and useful resources were: 1) homework problems, 2) class notes and 3) group studying. When working on math-based programming (Matlab and Mathcad) as well as computer-aided design, the most used and useful resources were: 1) group studying, 2) engineering tutoring center, and 3) undergraduate teaching assistants. Concerning learning concepts and exams in the BME department, homework problems and class notes were considered some of the highest-ranking resources for both frequency and usefulness. When comparing to the pilot study in MSE, both BME and MSE students tend to highly favor peer mentors and old exams as a means of studying for exams at the end of the semester1. Because the MSE course only considered exams, we cannot make any comparisons to BME data concerning programming and CAD. This analysis has highlighted potential resources that are universally beneficial, such as the use of peer work, i.e. group studying, engineering tutoring center, and teaching assistants; however, we see differences by both discipline and topical area thereby highlighting the need to determine important resources on a class-by-class basis as well.
ContributorsMalkoc, Aldin (Author) / Ankeny, Casey (Thesis director) / Krause, Stephen (Committee member) / Harrington Bioengineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
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Description
The role of retention and forgetting of context dependent sensorimotor memory of dexterous manipulation was explored. Human subjects manipulated a U-shaped object by switching the handle to be grasped (context) three times, and then came back two weeks later to lift the same object in the opposite context relative to

The role of retention and forgetting of context dependent sensorimotor memory of dexterous manipulation was explored. Human subjects manipulated a U-shaped object by switching the handle to be grasped (context) three times, and then came back two weeks later to lift the same object in the opposite context relative to that experience on the last block. On each context switch, an interference of the previous block of trials was found resulting in manipulation errors (object tilt). However, no significant re-learning was found two weeks later for the first block of trials (p = 0.826), indicating that the previously observed interference among contexts lasted a very short time. Interestingly, upon switching to the other context, sensorimotor memories again interfered with visually-based planning. This means that the memory of lifting in the first context somehow blocked the memory of lifting in the second context. In addition, the performance in the first trial two weeks later and the previous trial of the same context were not significantly different (p = 0.159). This means that subjects are able to retain long-term sensorimotor memories. Lastly, the last four trials in which subjects switched contexts were not significantly different from each other (p = 0.334). This means that the interference from sensorimotor memories of lifting in opposite contexts was weaker, thus eventually leading to the attainment of steady performance.
ContributorsGaw, Nathan Benjamin (Author) / Santello, Marco (Thesis director) / Helms Tillery, Stephen (Committee member) / Buneo, Christopher (Committee member) / Barrett, The Honors College (Contributor) / School of Mathematical and Statistical Sciences (Contributor) / Harrington Bioengineering Program (Contributor)
Created2013-05