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- All Subjects: engineering
- All Subjects: Semiconductors
- Creators: Goryll, Michael
Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Carrier lifetime is one of the few parameters which can give information about the low defect densities in today's semiconductors. In principle there is no lower limit to the defect density determined by lifetime measurements. No other technique can easily detect defect densities as low as 10-9 - 10-10 cm-3 in a simple, contactless room temperature measurement. However in practice, recombination lifetime τr measurements such as photoconductance decay (PCD) and surface photovoltage (SPV) that are widely used for characterization of bulk wafers face serious limitations when applied to thin epitaxial layers, where the layer thickness is smaller than the minority carrier diffusion length Ln. Other methods such as microwave photoconductance decay (µ-PCD), photoluminescence (PL), and frequency-dependent SPV, where the generated excess carriers are confined to the epitaxial layer width by using short excitation wavelengths, require complicated configuration and extensive surface passivation processes that make them time-consuming and not suitable for process screening purposes. Generation lifetime τg, typically measured with pulsed MOS capacitors (MOS-C) as test structures, has been shown to be an eminently suitable technique for characterization of thin epitaxial layers. It is for these reasons that the IC community, largely concerned with unipolar MOS devices, uses lifetime measurements as a "process cleanliness monitor." However when dealing with ultraclean epitaxial wafers, the classic MOS-C technique measures an effective generation lifetime τg eff which is dominated by the surface generation and hence cannot be used for screening impurity densities. I have developed a modified pulsed MOS technique for measuring generation lifetime in ultraclean thin p/p+ epitaxial layers which can be used to detect metallic impurities with densities as low as 10-10 cm-3. The widely used classic version has been shown to be unable to effectively detect such low impurity densities due to the domination of surface generation; whereas, the modified version can be used suitably as a metallic impurity density monitoring tool for such cases.
ContributorsElhami Khorasani, Arash (Author) / Alford, Terry (Thesis advisor) / Goryll, Michael (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2013
Description
Photodetectors in the 1.7 to 4.0 μm range are being commercially developed on InP substrates to meet the needs of longer wavelength applications such as thermal and medical sensing. Currently, these devices utilize high indium content metamorphic Ga1-xInxAs (x > 0.53) layers to extend the wavelength range beyond the 1.7 μm achievable using lattice matched GaInAs. The large lattice mismatch required to reach the extended wavelengths results in photodetector materials that contain a large number of misfit dislocations. The low quality of these materials results in a large nonradiative Shockley Read Hall generation/recombination rate that is manifested as an undesirable large thermal noise level in these photodetectors. This work focuses on utilizing the different band structure engineering methods to design more efficient devices on InP substrates. One prospective way to improve photodetector performance at the extended wavelengths is to utilize lattice matched GaInAs/GaAsSb structures that have a type-II band alignment, where the ground state transition energy of the superlattice is smaller than the bandgap of either constituent material. Over the extended wavelength range of 2 to 3 μm this superlattice structure has an optimal period thickness of 3.4 to 5.2 nm and a wavefunction overlap of 0.8 to 0.4, respectively. In using a type-II superlattice to extend the cutoff wavelength there is a tradeoff between the wavelength reached and the electron-hole wavefunction overlap realized, and hence absorption coefficient achieved. This tradeoff and the subsequent reduction in performance can be overcome by two methods: adding bismuth to this type-II material system; applying strain on both layers in the system to attain strain-balanced condition. These allow the valance band alignment and hence the wavefunction overlap to be tuned independently of the wavelength cutoff. Adding 3% bismuth to the GaInAs constituent material, the resulting lattice matched Ga0.516In0.484As0.970Bi0.030/GaAs0.511Sb0.489superlattice realizes a 50% larger absorption coefficient. While as, similar results can be achieved with strain-balanced condition with strain limited to 1.9% on either layer. The optimal design rules derived from the different possibilities make it feasible to extract superlattice period thickness with the best absorption coefficient for any cutoff wavelength in the range.
ContributorsSharma, Ankur R (Author) / Johnson, Shane (Thesis advisor) / Goryll, Michael (Committee member) / Roedel, Ronald (Committee member) / Arizona State University (Publisher)
Created2013
Description
The Metal Semiconductor Field Effect Transistor (MESFET) has high potential to enter analog and RF applications due to their high breakdown voltage and switching frequency characteristics. These MESFET devices could allow for high voltage analog circuits to be integrated with low voltage digital circuits on a single chip in an extremely cost effective way. Higher integration leads to electronics with increased functionality and a smaller finished product. The MESFETs are designed in-house by the research group led by Dr. Trevor Thornton. The layouts are then sent to multi-project wafer (MPW) integrated circuit foundry companies, such as the Metal Oxide Semiconductor Implementation Service (MOSIS) to be fabricated. Once returned, the electrical characteristics of the devices are measured. The MESFET has been implemented in various applications by the research group, including the low dropout linear regulator (LDO) and RF power amplifier. An advantage of the MESFET is that it can function in extreme environments such as space, allowing for complex electrical systems to continue functioning properly where traditional transistors would fail.
ContributorsKam, Jason (Author) / Thornton, Trevor (Thesis director) / Goryll, Michael (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2015-05
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
With the progression of different industries moving away from employing secretaries for business professionals and professors, there exists a void in the area of personal assistance. This problem has existing solutions readily available to replace this service, i.e. secretary or personal assistant, tend to range from expensive and useful to inexpensive and not efficient. This leaves a low cost niche into the market of a virtual office assistant or manager to display messages and to help direct people in obtaining contact information. The development of a low cost solution revolves around the software needed to solve the various problems an accessible and user friendly Virtual Interface in which the owner of the Virtual Office Manager/Assistant can communicate to colleagues who are at standby outside of the owner's office and vice versa. This interface will be allowing the owner to describe the status pertaining to their absence or any other message sent to the interface. For example, the status of the owner's work commute can be described with a simple "Running Late" phrase or a message like "Busy come back in 10 minutes". In addition, any individual with an interest to these entries will have the opportunity to respond back because the device will provide contact information. When idle, the device will show supplemental information such as the owner's calendar and name. The scope of this will be the development and testing of solutions to achieve these goals.
ContributorsOffenberger, Spencer Eliot (Author) / Kozicki, Michael (Thesis director) / Goryll, Michael (Committee member) / Electrical Engineering Program (Contributor) / Computer Science and Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-12
Description
In-field characterization of photovoltaics is crucial to understanding performance and degradation mechanisms, subsequently improving overall reliability and lifespans. Current outdoor characterization is often limited by logistical difficulties, variable weather, and requirements to measure during peak production hours. It becomes a challenge to find a characterization technique that is affordable with a low impact on system performance while still providing useful device parameters. For added complexity, this characterization technique must have the ability to scale for implementation in large powerplant applications. This dissertation addresses some of the challenges of outdoor characterization by expanding the knowledge of a well-known indoor technique referred to as Suns-VOC. Suns-VOC provides a pseudo current-voltage curve that is free of any effects from series resistance. Device parameters can be extracted from this pseudo I-V curve, allowing for subsequent degradation analysis. This work introduces how to use Suns-VOC outdoors while normalizing results based on the different effects of environmental conditions. This technique is validated on single-cells, modules, and small arrays with accuracies capable of measuring yearly degradation. An adaptation to Suns-VOC, referred to as Suns-Voltage-Resistor (Suns-VR), is also introduced to complement the results from Suns-VOC. This work can potentially be used to provide a diagnostic tool for outdoor characterization in various applications, including residential, commercial, and industrial PV systems.
ContributorsKillam, Alexander Cameron (Author) / Bowden, Stuart G (Thesis advisor) / Goryll, Michael (Committee member) / Augusto, Andre (Committee member) / Rand, James (Committee member) / Arizona State University (Publisher)
Created2022
Description
To keep up with the increasing demand for solar energy, higher efficiencies are necessary while keeping cost at a minimum. The easiest theoretical way to achieve that is using silicon-based multi-junction solar cells. However, there are major challenges in effectively implementing such a system. Much work has been done recently to integrate III-V with Si for multi-junction solar cell purposes. The focus of this paper is to explore GaP-based dilute nitrides as a possible top cell candidate for Si-based multi-junctions. The direct growth of dilute nitrides in a lattice-matched configuration epitaxially in literature is reviewed. The problems associated with such growths are outlined and pathways to mitigate these problems are presented. The need for a GaP buffer layer between the dilute nitride film and Si is established. Defects in GaP/Si system are explored in detail and a study on pit formation during such growth is performed. Effective suppression of pits in GaP surface grown on Si is achieved. Issues facing GaP-based dilute nitrides in terms of material properties are outlined. Review of these challenges is done and some possible future areas of interest to improve material quality are established. Finally, the growth process of dilute nitrides using Molecular Beam Epitaxy tool is explained. Results for GaNP grown on Si pre and post growth treatments are detailed.
ContributorsMurali, Srinath (Author) / Honsberg, Christiana (Thesis advisor) / Goodnick, Stephen (Committee member) / King, Richard (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2022
Description
In this dissertation, the nanofabrication process is characterized for fabrication of nanostructure on surface of silicon and gallium phosphide using silica nanosphere lithography (SNL) and metal assisted chemical etching (MACE) process. The SNL process allows fast process time and well defined silica nanosphere monolayer by spin-coating process after mixing N,N-dimethyl-formamide (DMF) solvent. The MACE process achieves the high aspect ratio structure fabrication using the reaction between metal and wet chemical. The nanostructures are fabricated on Si surface for enhanced light management, but, without proper surface passivation those gains hardly impact the performance of the solar cell. The surface passivation of nanostructures is challenging, not only due to larger surface areas and aspect ratios, but also has a direct result of the nanofabrication processes. In this research, the surface passivation of silicon nanostructures is improved by modifying the silica nanosphere lithography (SNL) and the metal assisted chemical etching (MACE) processes, frequently used to fabricate nanostructures. The implementation of a protective silicon oxide layer is proposed prior to the lithography process to mitigate the impact of the plasma etching during the SNL. Additionally, several adhesion layers are studied, chromium (Cr), nickel (Ni) and titanium (Ti) with gold (Au), used in the MACE process. The metal contamination is one of main damage and Ti makes the mitigation of metal contamination. Finally, a new chemical etching step is introduced, using potassium hydroxide at room temperature, to smooth the surface of the nanostructures after the MACE process. This chemical treatment allows to improve passivation by surface area control and removing surface defects. In this research, I demonstrate the Aluminum Oxide (Al2O3) passivation on nanostructure using atomic layer deposition (ALD) process. 10nm of Al2O3 layer makes effective passivation on nanostructure with optimized post annealing in forming gas (N2/H2) environment. However, 10nm thickness is not suitable for hetero structure because of carrier transportation. For carrier transportation, ultrathin Al2O3 (≤ 1nm) layer is used for passivation, but effective passivation is not achieved because of insufficient hydrogen contents. This issue is solved to use additional ultrathin SiO2 (1nm) below Al2O3 layer and hydrogenation from doped a-Si:H.
Moreover, the nanostructure is creased on gallium phosphide (GaP) by SNL and MACE process. The fabrication process is modified by control of metal layer and MACE solution.
ContributorsKim, Sangpyeong (Author) / Honsberg, Christiana (Thesis advisor) / Bowden, Stuart (Committee member) / Goryll, Michael (Committee member) / Augusto, Andre (Committee member) / Arizona State University (Publisher)
Created2021
Description
A general review of film growth with various mechanisms is given. Additives and their potential effects on film properties are also discussed. Experimental light-induced aluminum (Al) plating tool design is discussed. Light-induced electroplating of Al as the front electrode on the n-type emitter of silicon (Si) solar cells is proposed as a substitute for screen-printed Silver (Ag). The advantages and disadvantages of Al over copper (Cu) as a suitable Ag replacement are examined. Optimization of the power given to a green laser for silicon nitride (SiNx) anitreflection coating patterning is performed. Laser damage and contamination removal conditions on post-patterned cell surfaces are identified. Plating and post-annealing temperature effects on Al morphology and film resistivity are explored. Morphology and resistivity improvement of the Al film are also investigated through several plating additives. The lowest resistivity of 3.1 µΩ-cm is given by nicotinic acid. Laser induced damage to the cell emitter experimentally limits the contact resistivity between light-induced Al and Si to approximately 69 mΩ-cm2. Phosphorus pentachloride (PCl5) is introduced into the plating bath and improved the the contact resistivity between light induced Al and Si to a range of 0.1-1 mΩ-cm2. Secondary ion mass spectroscopy (SIMS) was performed on a film deposited with PCl5 and showed a phosphorus peak, indicating emitter phosphorus concentration may be the reason for the low contact resistivity between light-induced Al and Si. SEM also shows that PCl5 improves Al film density and plating throwing power. Post plating annealing performed at a temperature of 500°C allows Al to spike through the thin n-type emitter causing cell failure. Atmospheric moisture causes poor process reproducibility.
ContributorsRicci, Lewis (Author) / Tao, Meng (Thesis advisor) / Goryll, Michael (Committee member) / Kozicki, Michael (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2021