Matching Items (13)
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- All Subjects: engineering
- Genre: Masters Thesis
- Creators: Bakkaloglu, Bertan
- Member of: Theses and Dissertations
Description
Current hybrid vehicle and/or Fuel Cell Vehicle (FCV) use both FC and an electric system. The sequence of the electric power train with the FC system is intended to achieve both better fuel economies than the conventional vehicles and higher performance. Current hybrids use regenerative braking technology, which converts the vehicles kinetic energy into electric energy instead of wasting it. A hybrid vehicle is much more fuel efficient than conventional Internal Combustion (IC) engine and has less environmental impact The new hybrid vehicle technology with it's advanced with configurations (i.e. Mechanical intricacy, advanced driving modes etc) inflict an intrusion with the existing Thermal Management System (TMS) of the conventional vehicles. This leaves for the opportunity for now thermal management issues which needed to be addressed. Till date, there has not been complete literature on thermal management issued of FC vehicles. The primary focus of this dissertation is on providing better cooling strategy for the advanced power trains. One of the cooling strategies discussed here is the thermo-electric modules.
The 3D Thermal modeling of the FC stack utilizes a Finite Differencing heat approach method augmented with empirical boundary conditions is employed to develop 3D thermal model for the integration of thermoelectric modules with Proton Exchange Membrane fuel cell stack. Hardware-in-Loop was designed under pre-defined drive cycle to obtain fuel cell performance parameters along with anode and cathode gas flow-rates and surface temperatures. The FC model, combined experimental and finite differencing nodal net work simulation modeling approach which implemented heat generation across the stack to depict the chemical composition process. The structural and temporal temperature contours obtained from this model are in compliance with the actual recordings obtained from the infrared detector and thermocouples. The Thermography detectors were set-up through dual band thermography to neutralize the emissivity and to give several dynamic ranges to achieve accurate temperature measurements. The thermocouples network was installed to provide a reference signal.
The model is harmonized with thermo-electric modules with a modeling strategy, which enables optimize better temporal profile across the stack. This study presents the improvement of a 3D thermal model for proton exchange membrane fuel cell stack along with the interfaced thermo-electric module. The model provided a virtual environment using a model-based design approach to assist the design engineers to manipulate the design correction earlier in the process and eliminate the need for costly and time consuming prototypes.
The 3D Thermal modeling of the FC stack utilizes a Finite Differencing heat approach method augmented with empirical boundary conditions is employed to develop 3D thermal model for the integration of thermoelectric modules with Proton Exchange Membrane fuel cell stack. Hardware-in-Loop was designed under pre-defined drive cycle to obtain fuel cell performance parameters along with anode and cathode gas flow-rates and surface temperatures. The FC model, combined experimental and finite differencing nodal net work simulation modeling approach which implemented heat generation across the stack to depict the chemical composition process. The structural and temporal temperature contours obtained from this model are in compliance with the actual recordings obtained from the infrared detector and thermocouples. The Thermography detectors were set-up through dual band thermography to neutralize the emissivity and to give several dynamic ranges to achieve accurate temperature measurements. The thermocouples network was installed to provide a reference signal.
The model is harmonized with thermo-electric modules with a modeling strategy, which enables optimize better temporal profile across the stack. This study presents the improvement of a 3D thermal model for proton exchange membrane fuel cell stack along with the interfaced thermo-electric module. The model provided a virtual environment using a model-based design approach to assist the design engineers to manipulate the design correction earlier in the process and eliminate the need for costly and time consuming prototypes.
ContributorsRamani, Dilip (Author) / Mayyas, Abdel Ra'Ouf (Thesis advisor) / Hsu, Keng (Committee member) / Madakannan, Arunachalanadar (Committee member) / Arizona State University (Publisher)
Created2014
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
The demand for miniaturized components with feature sizes as small as tens of microns and tolerances as small as 0.1 microns is on the rise in the fields of aerospace, electronics, optics and biomedical engineering. Micromilling has proven to be a process capable of generating the required accuracy for these features and is an alternative to various non-mechanical micro-manufacturing processes which are limited in terms of cost and productivity, especially at the micro-meso scale. The micromilling process is on the surface, a miniaturized version of conventional milling, hence inheriting its benefits. However, the reduction in scale by a few magnitudes makes the process peculiar and unique; and the macro-scale theories have failed to successfully explain the micromilling process and its machining parameters. One such characteristic is the unpredictable nature of tool wear and breakage. There is a large cost benefit that can be realized by improving tool life. Workpiece rejection can also be reduced by successfully monitoring the condition of the tool to avoid issues. Many researchers have developed Tool Condition Monitoring and Tool Wear Modeling systems to address the issue of tool wear, and to obtain new knowledge. In this research, a tool wear modeling effort is undertaken with a new approach. A new tool wear signature is used for real-time data collection and modeling of tool wear. A theoretical correlation between the number of metal chips produced during machining and the condition of the tool is introduced. Experimentally, it is found that the number of chips produced drops with respect to the feedrate of the cutting process i.e. when the uncut chip thickness is below the theoretical minimum chip thickness.
ContributorsBajaj, Anuj Kishorkumar (Author) / SODEMANN, ANGELA A (Thesis advisor) / Bekki, Jeniffer (Committee member) / Hsu, Keng (Committee member) / Arizona State University (Publisher)
Created2015
Description
Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
ContributorsBakliwal, Priyanka (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
Description
The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
ContributorsDesai, Chirag (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016
Description
Determining the thermal conductivity of carbon gas diffusion layers used in hydrogen fuel cells is a very active topic of research. The primary driver behind this research is due to the need for development of proton exchange membrane fuels with longer usable life cycles before failure. As heat is a byproduct of the oxygen-hydrogen reaction an optimized pathway to remove the excess heat is needed to prevent thermal damage to the fuel cell as both mechanical and chemical degradation is accelerated under elevated temperatures. Commercial systems used for testing thermal conductivity are readily available, but are prohibitively expensive, ranging from just over $10,000 to $80,000 for high-end systems. As this cost can exclude some research labs from experimenting with thermal conductivity, a low cost alternative system is a desirable product. The development of a low cost system that maintained typical accuracy levels of commercials systems was carried out successfully at a significant cost reduction. The end product was capable of obtaining comparable accuracy to commercial systems at a cost reduction of more than 600% when compared to entry level commercial models. Combined with a system design that only required some basic fabrication equipment, this design will allow many research labs to expand their testing capabilities without straining departmental budgets. As expected with the development of low cost solutions, the reduction in cost came at the loss in other aspects of system performance, mainly run time. While the developed system requires a significate time investment to obtain useable results, the system can be improved by the used of RTDs in place of thermocouples or incorporation of an isothermal cold plate. These improvements would reduce the runtime to less than that of a standard work day while maintaining an approximate reduction in cost of 350%.
ContributorsSucher, Brent (Author) / Kannan, Arunachala (Thesis advisor) / Hsu, Keng (Committee member) / Nam, Changho (Committee member) / Arizona State University (Publisher)
Created2016
Description
This thesis presents a power harvesting system combining energy from sub-cells of
multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost
converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor current
regulation in designed to reduce cross regulation caused by inductor-sharing in CCM. A
modified hill-climbing algorithm is implemented to achieve maximum power point
tracking (MPPT). A dual-path architecture is implemented to provide a regulated 1.8V
output. A proposed lossless current sensor monitors transient inductor current and a time-based power monitor is proposed to monitor PV power. The PV input provides power of
65mW. Measured results show that the peak efficiency achieved is around 85%. The
power switches and control circuits are implemented in standard 0.18um CMOS process.
multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost
converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor current
regulation in designed to reduce cross regulation caused by inductor-sharing in CCM. A
modified hill-climbing algorithm is implemented to achieve maximum power point
tracking (MPPT). A dual-path architecture is implemented to provide a regulated 1.8V
output. A proposed lossless current sensor monitors transient inductor current and a time-based power monitor is proposed to monitor PV power. The PV input provides power of
65mW. Measured results show that the peak efficiency achieved is around 85%. The
power switches and control circuits are implemented in standard 0.18um CMOS process.
ContributorsPeng, Qirong (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2017
Description
With the growing popularity of 3d printing in recreational, research, and commercial enterprises new techniques and processes are being developed to improve the quality of parts created. Even so, the anisotropic properties is still a major hindrance of parts manufactured in this method. The goal is to produce parts that mimic the strength characteristics of a comparable part of the same design and materials created using injection molding. In achieving this goal the production cost can be reduced by eliminating the initial investment needed for the creation of expensive tooling. This initial investment reduction will allow for a wider variant of products in smaller batch runs to be made available. This thesis implements the use of ultraviolet (UV) illumination for an in-process laser local pre-deposition heating (LLPH). By comparing samples with and without the LLPH process it is determined that applied energy that is absorbed by the polymer is converted to an increase in the interlayer temperature, and resulting in an observed increase in tensile strength over the baseline test samples. The increase in interlayer bonding thus can be considered the dominating factor over polymer degradation.
ContributorsKusel, Scott Daniel (Author) / Hsu, Keng (Thesis advisor) / Sodemann, Angela (Committee member) / Kannan, Arunachala M (Committee member) / Arizona State University (Publisher)
Created2017
Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps.
ContributorsMartino, Todd Jeffrey (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2010