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- All Subjects: engineering
- Genre: Academic theses
- Creators: Bakkaloglu, Bertan
- Member of: Theses and Dissertations
Perpetual Pavements, if properly designed and rehabilitated, it can last longer than 50 years without major structural rehabilitation. Fatigue endurance limit is a key parameter for designing perpetual pavements to mitigate bottom-up fatigue cracking. The endurance limit has not been implemented in the Mechanistic Empirical Pavement Design Guide software, currently known as DARWin-ME. This study was conducted as part of the National Cooperative Highway Research Program (NCHRP) Project 9-44A to develop a framework and mathematical methodology to determine the fatigue endurance limit using the uniaxial fatigue test. In this procedure, the endurance limit is defined as the allowable tensile strains at which a balance takes place between the fatigue damage during loading, and the healing during the rest periods between loading pulses. The viscoelastic continuum damage model was used to isolate time dependent damage and healing in hot mix asphalt from that due to fatigue. This study also included the development of a uniaxial fatigue test method and the associated data acquisition computer programs to conduct the test with and without rest period. Five factors that affect the fatigue and healing behavior of asphalt mixtures were evaluated: asphalt content, air voids, temperature, rest period and tensile strain. Based on the test results, two Pseudo Stiffness Ratio (PSR) regression models were developed. In the first model, the PSR was a function of the five factors and the number of loading cycles. In the second model, air voids, asphalt content, and temperature were replaced by the initial stiffness of the mix. In both models, the endurance limit was defined when PSR is equal to 1.0 (net damage is equal to zero). The results of the first model were compared to the results of a stiffness ratio model developed based on a parallel study using beam fatigue test (part of the same NCHRP 9-44A). The endurance limit values determined from uniaxial and beam fatigue tests showed very good correlation. A methodology was described on how to incorporate the second PSR model into fatigue analysis and damage using the DARWin-ME software. This would provide an effective and efficient methodology to design perpetual flexible pavements.
Asphalt concrete is the most recycled material in the United States and its reclamation allows the positive reuse of the constituent aggregates and asphalt binder, contributing to the long-term sustainability of the transportation infrastructure; decreasing costs, and the total energy and greenhouse emissions embodied into new materials and infrastructure. Although the national trends in Reclaimed Asphalt Pavements (RAP) usage are encouraging, the environmental conditions in Phoenix, Arizona are extreme and needs further consideration.
The objective of this research study was to evaluate the viability of using RAP in future pavement maintenance and rehabilitation projects for the City. Agencies in the State of Arizona have been slow adopting the use of RAP as a regular practice. While the potential benefits are great, there is some concern on the impact to long-term pavement performance.
RAP millings were sampled from the city’s stockpiles; processed RAP and virgin materials were provided by a local plant. Two asphalt binders were used: PG 70-10 and PG 64-16. RAP variability was evaluated by aggregate gradations; extracted and recovered binder was tested for properties and grading.
A mixture design procedure based on the City’s specifications was defined to establish trial blends. RAP incorporation was based on national and local practices. Four different RAP contents were studied 10%, 15%, 25%, and 25% content with a softer binder, in addition to a control mix (0% RAP).
Performance tests included: dynamic modulus to evaluate stiffness; Flow Number, to assess susceptibility for permanent deformation (rutting); and Tensile Strength Ratio as a measure of susceptibility to moisture damage.
Binder testing showed very stiff recovered asphalts and variable contents with a reasonable variability on aggregate gradations. Performance test results showed slightly higher modulus as RAP content increases, showing a slight improvement related to rutting as well. For moisture damage potential, all mixtures performed well showing improvement for RAP mixtures in most cases.
Statistical analysis showed that 0%, 10%, 15% and 25% with softer binder do not present significant statistical difference among mixtures, indicating that moderate RAP contents are feasible to use within the City paving operations and will not affect greatly nor negatively the pavement performance.
The objective of the research is to test the use of 3D printed thermoplastic to produce fixtures which affix instrumentation to asphalt concrete samples used for Simple Performance Testing (SPT). The testing is done as part of materials characterization to obtain properties that will help in future pavement designs. Currently, these fixtures (mounting studs) are made of expensive brass and cumbersome to clean with or without chemicals.
Three types of thermoplastics were utilized to assess the effect of temperature and applied stress on the performance of the 3D printed studs. Asphalt concrete samples fitted with thermoplastic studs were tested according to AASHTO & ASTM standards. The thermoplastics tested are: Polylactic acid (PLA), the most common 3D printing material; Acrylonitrile Butadiene Styrene (ABS), a typical 3D printing material which is less rigid than PLA and has a higher melting temperature; Polycarbonate (PC), a strong, high temperature 3D printing material.
A high traffic volume Marshal mix design from the City of Phoenix was obtained and adapted to a Superpave mix design methodology. The mix design is dense-graded with nominal maximum aggregate size of ¾” inch and a PG 70-10 binder. Samples were fabricated and the following tests were performed: Dynamic Modulus |E*| conducted at five temperatures and six frequencies; Flow Number conducted at a high temperature of 50°C, and axial cyclic fatigue test at a moderate temperature of 18°C.
The results from SPT for each 3D printed material were compared to results using brass mounting studs. Validation or rejection of the concept was determined from statistical analysis on the mean and variance of collected SPT test data.
The concept of using 3D printed thermoplastic for mounting stud fabrication is a promising option; however, the concept should be verified with more extensive research using a variety of asphalt mixes and operators to ensure no bias in the repeatability and reproducibility of test results. The Polycarbonate (PC) had a stronger layer bonding than ABS and PLA while printing. It was recommended for follow up studies.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.