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Description
Microelectronic industry is continuously moving in a trend requiring smaller and smaller devices and reduced form factors with time, resulting in new challenges. Reduction in device and interconnect solder bump sizes has led to increased current density in these small solders. Higher level of electromigration occurring due to increased current

Microelectronic industry is continuously moving in a trend requiring smaller and smaller devices and reduced form factors with time, resulting in new challenges. Reduction in device and interconnect solder bump sizes has led to increased current density in these small solders. Higher level of electromigration occurring due to increased current density is of great concern affecting the reliability of the entire microelectronics systems. This paper reviews electromigration in Pb- free solders, focusing specifically on Sn0.7wt.% Cu solder joints. Effect of texture, grain orientation, and grain-boundary misorientation angle on electromigration and intermetallic compound (IMC) formation is studied through EBSD analysis performed on actual C4 bumps.
ContributorsLara, Leticia (Author) / Tasooji, Amaneh (Thesis advisor) / Lee, Kyuoh (Committee member) / Krause, Stephen (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Ball Grid Array (BGA) using lead-free or lead-rich solder materials are widely used as Second Level Interconnects (SLI) in mounting packaged components to the printed circuit board (PCB). The reliability of these solder joints is of significant importance to the performance of microelectronics components and systems. Product design/form-factor, solder material,

Ball Grid Array (BGA) using lead-free or lead-rich solder materials are widely used as Second Level Interconnects (SLI) in mounting packaged components to the printed circuit board (PCB). The reliability of these solder joints is of significant importance to the performance of microelectronics components and systems. Product design/form-factor, solder material, manufacturing process, use condition, as well as, the inherent variabilities present in the system, greatly influence product reliability. Accurate reliability analysis requires an integrated approach to concurrently account for all these factors and their synergistic effects. Such an integrated and robust methodology can be used in design and development of new and advanced microelectronics systems and can provide significant improvement in cycle-time, cost, and reliability. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks of (1) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, (2) Finite Element analysis (FEM) to predict system response needed for life prediction, and (3) development of a probabilistic methodology to predict the reliability, as well as, the sensitivity of the system to various parameters and the variabilities. These tasks and the predictive capabilities of IMPRPK in microelectronic reliability analysis are discussed.
ContributorsFallah-Adl, Ali (Author) / Tasooji, Amaneh (Thesis advisor) / Krause, Stephen (Committee member) / Alford, Terry (Committee member) / Jiang, Hanqing (Committee member) / Mahajan, Ravi (Committee member) / Arizona State University (Publisher)
Created2013
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Description
This thesis discusses the evolution of conduction mechanism in the silver (Ag) on zinc oxide (ZnO) thin film system with respect to the Ag morphology. As a plausible substitute for indium tin oxide (ITO), TCO/Metal/TCO (TMT) structure has received a lot of attentions as a prospective ITO substitute due to

This thesis discusses the evolution of conduction mechanism in the silver (Ag) on zinc oxide (ZnO) thin film system with respect to the Ag morphology. As a plausible substitute for indium tin oxide (ITO), TCO/Metal/TCO (TMT) structure has received a lot of attentions as a prospective ITO substitute due to its low resistivity and desirable transmittance. However, the detailed conduction mechanism is not fully understood. In an attempt to investigate the conduction mechanism of the ZnO/Ag/ZnO thin film system with respect to the Ag microstructure, the top ZnO layer is removed, which offers a better view of Ag morphology by using scanning electron microscopy (SEM). With 2 nm thick Ag layer, it is seen that the Ag forms discrete islands with small islands size (r), but large separation (s); also the effective resistivity of the system is extremely high. This regime is designated as dielectric zone. In this regime, thermionic emission and activated tunneling conduction mechanisms are considered. Based on simulations, when "s" was beyond 6 nm, thermionic emission dominates; with "s" less than 6 nm, activated tunneling is the dominating mechanism. As the Ag thickness increases, the individual islands coalesce and Ag clusters are formed. At certain Ag thickness, there are one or several Ag clusters that percolate the ZnO film, and the effective resistivity of the system exhibits a tremendous drop simultaneously, because the conducting electrons do not need to overcome huge ZnO barrier to transport. This is recognized as percolation zone. As the Ag thickness grows, Ag film becomes more continuous and there are no individual islands left on the surface. The effective resistivity decreases and is comparable to the characteristics of metallic materials, so this regime is categorized as metallic zone. The simulation of the Ag thin film resistivity is performed in terms of Ag thickness, and the experimental data fits the simulation well, which supports the proposed models. Hall measurement and four point probe measurement are carried out to characterize the electrical properties of the thin film system.
ContributorsZhang, Shengke (Author) / Alford, Terry L. (Thesis advisor) / Schroder, Dieter K. (Committee member) / Tasooji, Amaneh (Committee member) / Arizona State University (Publisher)
Created2012
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Description
This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20µm to 100µm with

This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20µm to 100µm with an aspect ratio of 0.5 to 1.5 and fine line patterns defined by photolithography. Photolithography defined pattern regions incorporate a wide variety of feature sizes including large circular pad structures with diameter of 20µm - 200µm, fine traces with varying widths of 3µm - 30µm and additional planar regions to define a IC substrate package. Electrodeposition of copper is performed to establish the desired circuit. Electrodeposition of copper in IC substrate applications holds certain unique challenges in that they require a low cost manufacturing process that enables a void-free gap fill inside the microvia along with uniform deposition of copper on exposed patterned regions. Deposition time scales to establish the desired metal thickness for such packages could range from several minutes to few hours. This work showcases a reverse pulse electrodeposition methodology that achieves void-free gap fill inside the microvia and uniform plating in FLS (Fine Lines and Spaces) regions with significantly higher deposition rates than traditional approaches. In order to achieve this capability, systematic experimental and simulation studies were performed. A strong correlation of independent parameters that govern the electrodeposition process such as bath temperature, reverse pulse plating parameters and the ratio of electrolyte concentrations is shown to the deposition kinetics and deposition uniformity in fine patterned regions and gap fill rate inside the microvia. Additionally, insight into the physics of via fill process is presented with secondary and tertiary current simulation efforts. Such efforts lead to show “smart” control of deposition rate at the top and bottom of via to avoid void formation. Finally, a parametric effect on grain size and the ensuing copper metallurgical characteristics of bulk copper is also shown to enable high reliability substrate packages for the IC packaging industry.
ContributorsGanesan, Kousik (Author) / Tasooji, Amaneh (Thesis advisor) / Manepalli, Rahul (Committee member) / Alford, Terry (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2018
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Description
The microstructure development of Inconel alloy 718 (IN718) during conventional processing has been extensively studied and much has been discovered as to the mechanisms behind the exceptional creep resistance that the alloy exhibits. More recently with the development of large scale 3D printing of alloys such as IN718 a new

The microstructure development of Inconel alloy 718 (IN718) during conventional processing has been extensively studied and much has been discovered as to the mechanisms behind the exceptional creep resistance that the alloy exhibits. More recently with the development of large scale 3D printing of alloys such as IN718 a new dimension of complexity has emerged in the understanding of alloy microstructure development, hence, potential alloy development opportunity for IN718.

This study is a broad stroke at discovering possible alternate microstructures developing in Direct-Metal-Laser-Sintering (DMLS) processed IN718 compared to those in conventional wrought IN718. The main inspiration for this study came from creep test results from several DMLS IN718 samples at Honeywell that showed a significant

improvement in creep capabilities for DMLS718 compared to cast and wrought IN718 (Honeywell).

From this data the steady-state creep rates were evaluated and fitted to current creep models in order to identify active creep mechanisms in conventional and DMLS IN718 and illuminate the potential factors responsible for the improved creep behavior in DMSL processed IN718.

Because rapid heating and cooling can introduce high internal stress and impact microstructural development, such as gamma double prime formations (Oblak et al.), leading to differences in material behavior, DMLS and conventional IN718 materials are studied using SEM and TEM characterization to investigate sub-micron and/or nano-scale

microstructural differences developed in the DMLS samples as a result of their complex thermal history and internal stress.

The preliminary analysis presented in this body of work is an attempt to better understand the effect of DMLS processing in quest for development of optimization techniques for DMLS as a whole. A historical sketch of nickel alloys and the development of IN718 is given. A literature review detailing the microstructure of IN718 is presented. Creep data analysis and identification of active creep mechanisms are evaluated. High-resolution microstructural characterization of DMLS and wrought IN718 are discussed in detail throughout various chapters of this thesis. Finally, an initial effort in developing a processing model that would allow for parameter optimization is presented.
ContributorsRogers, Blake Kenton (Author) / Tasooji, Amaneh (Thesis advisor) / Petuskey, William (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2017