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- Creators: Vittal, Vijay
- Creators: Yu, Hongbin
Description
Dr. Jerold D. Ottley's twenty-five years leading the Mormon Tabernacle Choir resulted in many distinguished awards and recognitions for the ensemble. Included among these are two Platinum and three Gold records from the Recording Industry Association of America, an Emmy from the Academy of Television Arts and Sciences, and two Freedom Foundation Awards for service to the country. He conducted the Choir at two presidential inaugurations, Ronald Reagan's in 1981 and George H. W. Bush's in 1989, as well as performances at the 1984 Los Angeles Olympics Gala. He presided over eleven international tours to twenty-six countries and crisscrossed the United States for engagements in nearly every region of the country. Despite the awards, commendations, and increased recognition of the Choir, Ottley's greatest contributions were largely internal to the organization. Jerold Ottley is a skilled music educator, administrator, and emissary. Application of these proficiencies while at the helm of the Choir, led to what are, arguably, his three largest contributions: 1) as educator, he instituted in-service training for choir members, raising the level of their individual musicianship, thereby improving the technical level of the entire Choir; 2) as administrator, Ottley created policies and procedures that resulted in a more disciplined, refined ensemble; and 3) as emissary, he raised the ensemble's reputation among the general public and with music professionals. For the general public, he significantly broadened the Choir's repertoire and traveled frequently thereby reaching a wider audience. He secured greater respect among music professionals by inviting many of them to work directly with the Choir. The results were unparalleled. Ottley's twenty-five year tenure with the Choir is reflected in broader audiences, increased professional acceptance, added organizational discipline, and unprecedented musical proficiency. It is a notable legacy for a man who reportedly never felt comfortable as director of the Mormon Tabernacle Choir.
ContributorsArchibald, Lyle Jay (Author) / Gentry, Gregory (Thesis advisor) / Britton, David (Committee member) / DeMars, James (Committee member) / Doan, Jerry (Committee member) / Solis, Theodore (Committee member) / Arizona State University (Publisher)
Created2011
Description
Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for example at room temperature, InAs field effect transistor (FET) has electron mobility of 40,000 cm2/Vs more than 10 times of Si FET. This makes such materials promising for high speed nanowire FETs. With small bandgap, such as 0.354 eV for InAs and 1.52 eV for GaAs, it does not need high voltage to turn on such devices which leads to low power consumption devices. Another feature of direct bandgap allows their applications of optoelectronic devices such as avalanche photodiodes. However, there are challenges to face up. Due to their large surface to volume ratio, nanowire devices typically are strongly affected by the surface states. Although nanowires can be grown into single crystal structure, people observe crystal defects along the wires which can significantly affect the performance of devices. In this work, FETs made of two types of III-V nanowire, GaAs and InAs, are demonstrated. These nanowires are grown by catalyst-free MOCVD growth method. Vertically nanowires are transferred onto patterned substrates for coordinate calibration. Then electrodes are defined by e-beam lithography followed by deposition of contact metals. Prior to metal deposition, however, the substrates are dipped in ammonium hydroxide solution to remove native oxide layer formed on nanowire surface. Current vs. source-drain voltage with different gate bias are measured at room temperature. GaAs nanowire FETs show photo response while InAs nanowire FETs do not show that. Surface passivation is performed on GaAs FETs by using ammonium surfide solution. The best results on current increase is observed with around 20-30 minutes chemical treatment time. Gate response measurements are performed at room temperature, from which field effect mobility as high as 1490 cm2/Vs is extracted for InAs FETs. One major contributor for this is stacking faults defect existing along nanowires. For InAs FETs, thermal excitations observed from temperature dependent results which leads us to investigate potential barriers.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Ferry, David (Committee member) / Tracy, Clarence (Committee member) / Arizona State University (Publisher)
Created2011
Description
A systematic approach to composition has been used by a variety of composers to control an assortment of musical elements in their pieces. This paper begins with a brief survey of some of the important systematic approaches that composers have employed in their compositions, devoting particular attention to Pierre Boulez's Structures Ia . The purpose of this survey is to examine several systematic approaches to composition by prominent composers and their philosophy in adopting this type of approach. The next section of the paper introduces my own systematic approach to composition: the Take-Away System. The third provides several musical applications of the system, citing my work, Octulus for two pianos, as an example. The appendix details theorems and observations within the system for further study.
ContributorsHarbin, Doug (Author) / Hackbarth, Glenn (Thesis advisor) / DeMars, James (Committee member) / Etezady, Roshanne, 1973- (Committee member) / Rockmaker, Jody (Committee member) / Rogers, Rodney (Committee member) / Arizona State University (Publisher)
Created2011
Description
A workload-aware low-power neuromorphic controller for dynamic power and thermal management in VLSI systems is presented. The neuromorphic controller predicts future workload and temperature values based on the past values and CPU performance counters and preemptively regulates supply voltage and frequency. System-level measurements from stateof-the-art commercial microprocessors are used to get workload, temperature and CPU performance counter values. The controller is designed and simulated using circuit-design and synthesis tools. At device-level, on-chip planar inductors suffer from low inductance occupying large chip area. On-chip inductors with integrated magnetic materials are designed, simulated and fabricated to explore performance-efficiency trade offs and explore potential applications such as resonant clocking and on-chip voltage regulation. A system level study is conducted to evaluate the effect of on-chip voltage regulator employing magnetic inductors as the output filter. It is concluded that neuromorphic power controller is beneficial for fine-grained per-core power management in conjunction with on-chip voltage regulators utilizing scaled magnetic inductors.
ContributorsSinha, Saurabh (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Yu, Hongbin (Committee member) / Christen, Jennifer B. (Committee member) / Arizona State University (Publisher)
Created2011
Description
Recent changes in the energy markets structure combined with the conti-nuous load growth have caused power systems to be operated under more stressed conditions. In addition, the nature of power systems has also grown more complex and dynamic because of the increasing use of long inter-area tie-lines and the high motor loads especially those comprised mainly of residential single phase A/C motors. Therefore, delayed voltage recovery, fast voltage collapse and short term voltage stability issues in general have obtained significant importance in relia-bility studies. Shunt VAr injection has been used as a countermeasure for voltage instability. However, the dynamic and fast nature of short term voltage instability requires fast and sufficient VAr injection, and therefore dynamic VAr devices such as Static VAr Compensators (SVCs) and STATic COMpensators (STAT-COMs) are used. The location and size of such devices are optimized in order to improve their efficiency and reduce initial costs. In this work time domain dy-namic analysis was used to evaluate trajectory voltage sensitivities for each time step. Linear programming was then performed to determine the optimal amount of required VAr injection at each bus, using voltage sensitivities as weighting factors. Optimal VAr injection values from different operating conditions were weighted and averaged in order to obtain a final setting of the VAr requirement. Some buses under consideration were either assigned very small VAr injection values, or not assigned any value at all. Therefore, the approach used in this work was found to be useful in not only determining the optimal size of SVCs, but also their location.
ContributorsSalloum, Ahmed (Author) / Vittal, Vijay (Thesis advisor) / Heydt, Gerald (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
Description
This research work describes the design of a fault current limiter (FCL) using digital logic and a microcontroller based data acquisition system for an ultra fast pilot protection system. These systems have been designed according to the requirements of the Future Renewable Electric Energy Delivery and Management (FREEDM) system (or loop), a 1 MW green energy hub. The FREEDM loop merges advanced power electronics technology with information tech-nology to form an efficient power grid that can be integrated with the existing power system. With the addition of loads to the FREEDM system, the level of fault current rises because of increased energy flow to supply the loads, and this requires the design of a limiter which can limit this current to a level which the existing switchgear can interrupt. The FCL limits the fault current to around three times the rated current. Fast switching Insulated-gate bipolar transistor (IGBT) with its gate control logic implements a switching strategy which enables this operation. A complete simulation of the system was built on Simulink and it was verified that the FCL limits the fault current to 1000 A compared to more than 3000 A fault current in the non-existence of a FCL. This setting is made user-defined. In FREEDM system, there is a need to interrupt a fault faster or make intelligent deci-sions relating to fault events, to ensure maximum availability of power to the loads connected to the system. This necessitates fast acquisition of data which is performed by the designed data acquisition system. The microcontroller acquires the data from a current transformer (CT). Mea-surements are made at different points in the FREEDM system and merged together, to input it to the intelligent protection algorithm that has been developed by another student on the project. The algorithm will generate a tripping signal in the event of a fault. The developed hardware and the programmed software to accomplish data acquisition and transmission are presented here. The designed FCL ensures that the existing switchgear equipments need not be replaced thus aiding future power system expansion. The developed data acquisition system enables fast fault sensing in protection schemes improving its reliability.
ContributorsThirumalai, Arvind (Author) / Karady, George G. (Thesis advisor) / Vittal, Vijay (Committee member) / Hedman, Kory (Committee member) / Arizona State University (Publisher)
Created2011
Description
CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to the continual scaling of CMOS devices. In this work the three primary intrinsic variations sources are studied, including random dopant fluctuation (RDF), line-edge roughness (LER) and oxide thickness fluctuation (OTF). The research is focused on the modeling and simulation of those variations and their scaling trends. Besides the three variations, a time dependent variation source, Random Telegraph Noise (RTN) is also studied. Different from the other three variations, RTN does not contribute much to the total variation amount, but aggregate the worst case of Vth variations in CMOS. In this work a TCAD based simulation study on RTN is presented, and a new SPICE based simulation method for RTN is proposed for time domain circuit analysis. Process-induced variations arise from the imperfection in silicon fabrication, and vary from foundries to foundries. In this work the layout dependent Vth shift due to Rapid-Thermal Annealing (RTA) are investigated. In this work, we develop joint thermal/TCAD simulation and compact modeling tools to analyze performance variability under various layout pattern densities and RTA conditions. Moreover, we propose a suite of compact models that bridge the underlying RTA process with device parameter change for efficient design optimization.
ContributorsYe, Yun, Ph.D (Author) / Cao, Yu (Thesis advisor) / Yu, Hongbin (Committee member) / Song, Hongjiang (Committee member) / Clark, Lawrence (Committee member) / Arizona State University (Publisher)
Created2011
Description
Many of the works of Dominick Argento have been researched and analyzed, but his choral work Evensong: Of Love and Angels s has received limited attention thus far. Written in memoriam for his wife Carolyn Bailey Argento, Evensong draws its musical material from her initials C.B.A. These letters, translated into note names, form a conspicuous head motive that is present in each movement of the work, and it serves multiple functions: as a melodic feature, as the foundation for a twelve-tone row, and as a harmonic base. This paper provides an overview of the work's conception with specific relation to Argento's biographical details, compositional style, and work habits; a brief review of the critical reception of the work; and a succinct analysis of the form and cyclical materials found in each movement.
ContributorsPage, Carrie Leigh, 1980- (Author) / Rogers, Rodney (Thesis advisor) / DeMars, James (Committee member) / Levy, Benjamin (Committee member) / Oldani, Robert (Committee member) / Arizona State University (Publisher)
Created2011
Description
Everyday Arias for soprano and orchestra was composed largely in Arizona and completed in February 2011. The text was taken from a small collection of the composer's own poetry referencing her memories of life in rural Mississippi. Everyday Arias endeavors to elevate these prosaic experiences and settings to art, expressing the everyday as beautiful and worthy of artistic treatment. The primary compositional model for this work was Samuel Barber's Knoxville: Summer of 1915, but other influences included Charles Ives, Aaron Copland, Benjamin Britten, and Dominick Argento. Barber's and Argento's musical treatment of prose style seemed particularly appropriate to the goals of Everyday Arias. Ives and Copland used hymn tunes both to evoke certain associations of worship and as sources of interesting material. The vocal writing of all five composers was influential, but the orchestration techniques for winds are largely a product of studying Ives and Argento, while many string gestures are more obviously tied to Britten and - more historically - Debussy.The primary motive that weaves through the work features an ascending major second followed by a descending perfect fourth, in a long-short-long rhythmic pattern. As a melodic fragment, the motive is often inverted to a descending-ascending pattern, or distorted slightly by expanding the second interval to a perfect fifth, or used in retrograde. The motive was derived from the first measure of the melody "Toplady" (1830) by Thomas Hastings, better known as the hymn "Rock of Ages." In the first movement, the motive is used most frequently in sequences. The second movement treats the motive as a melodic element and as a unit in ostinati. The final movement humorously transforms it into a syncopated gesture to evoke ragtime.
ContributorsPage, Carrie Leigh (Composer) / Rogers, Rodney (Thesis advisor) / DeMars, James (Committee member) / Levy, Benjamin (Committee member) / Oldani, Robert (Committee member) / Arizona State University (Publisher)
Created2011
Description
The electric transmission grid is conventionally treated as a fixed asset and is operated around a single topology. Though several instances of switching transmission lines for corrective mechaism, congestion management, and minimization of losses can be found in literature, the idea of co-optimizing transmission with generation dispatch has not been widely investigated. Network topology optimization exploits the redundancies that are an integral part of the network to allow for improvement in dispatch efficiency. Although, the concept of a dispatchable network initially appears counterintuitive questioning the wisdom of switching transmission lines on a more regu-lar basis, results obtained in the previous research on transmission switching with a Direct Current Optimal Power Flow (DCOPF) show significant cost reductions. This thesis on network topology optimization with ACOPF emphasizes the need for additional research in this area. It examines the performance of network topology optimization in an Alternating Current (AC) setting and its impact on various parameters like active power loss and voltages that are ignored in the DC setting. An ACOPF model, with binary variables representing the status of transmission lines incorporated into the formulation, is written in AMPL, a mathematical programming language and this optimization problem is solved using the solver KNITRO. ACOPF is a non-convex, nonlinear optimization problem, making it a very hard problem to solve. The introduction of bi-nary variables makes ACOPF a mixed integer nonlinear programming problem, further increasing the complexity of the optimization problem. An iterative method of opening each transmission line individually before choosing the best solution has been proposed as a purely investigative approach to studying the impact of transmission switching with ACOPF. Economic savings of up to 6% achieved using this approach indicate the potential of this concept. In addition, a heuristic has been proposed to improve the computational efficiency of network topology optimization. This research also makes a comparative analysis between transmission switching in a DC setting and switching in an AC setting. Results presented in this thesis indicate significant economic savings achieved by controlled topology optimization, thereby reconfirming the need for further examination of this idea.
ContributorsPotluri, Tejaswi (Author) / Hedman, Kory (Thesis advisor) / Vittal, Vijay (Committee member) / Heydt, Gerald (Committee member) / Arizona State University (Publisher)
Created2011