Search Content

Matching Items (3)

Filtering by

All Subjects: Systems Engineering
All Subjects: Women
Resource Type: Text

System-level synthesis of dataplane subsystems for MPSoCs

Description

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.

ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)

Created2013

Intervention Strategies for the DoD Acquisition Process Using Simulation

Description

The current Enterprise Requirements and Acquisition Model (ERAM), a discrete event simulation of the major tasks and decisions within the DoD acquisition system, identifies several what-if intervention strategies to improve program completion time. However, processes that contribute to the program acquisition completion time were not explicitly identified in the simulation study. This research seeks to determine the acquisition processes that contribute significantly to total simulated program time in the acquisition system for all programs reaching Milestone C. Specifically, this research examines the effect of increased scope management, technology maturity, and decreased variation and mean process times in post-Design Readiness Review contractor activities by performing additional simulation analyses. Potential policies are formulated from the results to further improve program acquisition completion time.

ContributorsWorger, Danielle Marie (Author) / Wu, Teresa (Thesis director) / Shunk, Dan (Committee member) / Wirthlin, J. Robert (Committee member) / Industrial, Systems (Contributor) / Barrett, The Honors College (Contributor)

Created2013-05

Can Beauty Coexist with Brains? Perceptions of NFL Cheerleaders

Description

The definition of "beauty" can be interpreted in many ways but when defining it literally, it is considered as such: "a combination of qualities that pleases the intellect or moral sense" (Oxford Dictionaries). Beauty simply "pleases" the intellect; it does not say that intellect is a factor of beauty itself. Beauty is nice to look at, a mere pleasure to experience in the "moral sense." It does not have anything to do with one's actions, principles or intelligence, but instead the way one presents himself or herself. If someone is deemed as intellectual, does that mean they are not viewed as beautiful? Is that why beauty is rarely associated with brains and vice versa? Has a history of stereotypes and media interference convinced us that these two concepts cannot coexist? And what if we found out that they did? Could we take that person seriously? I decided to challenge the idea of beauty and brains, and see if beauty is in fact measured by its literal definition and controlled by its assumed stereotype, or if other factors apply when deciphering someone's "beauty." First, I will analyze the perceptions and stereotypes of engineers. By looking at the public opinion of both engineers and women engineers, I can show the common struggles engineers face. Next I will look at perceptions of cheerleaders, in particular, professional cheerleaders. Through analyzing current stereotypes and gender roles associated with these women in the spotlight, I can establish how opinions of these women are formed. I will also look at a survey of a sample of Arizona State University students in which we can confirm or deny the results found through research of previous studies. We will also be able to gather personal opinions about why these stereotypes exist and how to break them down. Finally, we will look at personal accounts of current or retired National Football League (NFL) cheerleaders. These will give first-hand examples of what it is like to be both a cheerleader and a woman in STEM (science, technology, engineering, and mathematics).

ContributorsSanders, Samantha Kaye (Author) / Hibner Koblitz, Ann (Thesis director) / Eaton, John (Committee member) / McCarville, Daniel R. (Committee member) / Industrial, Systems (Contributor) / Barrett, The Honors College (Contributor)

Created2013-05