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Description
A single solar cell provides close to 0.5 V output at its maximum power point, which is very
low for any electronic circuit to operate. To get rid of this problem, traditionally multiple
solar cells are connected in series to get higher voltage. The disadvantage of this approach
is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can
result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT)
at single solar cell level is the most efficient way to extract power from solar cell.
Power Management IC (MPIC) used to extract power from single solar cell, needs to
start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area
overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an
auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input.
The auxiliary supply powers up a MPPT converter followed by a regulated converter. At
the start up both the converters operate at 100 kHz clock with 80% duty cycle and system
output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up
circuit is turned off and the supply voltage for both the converters is derived from the system
output itself. In steady-state condition the system output is regulated to 3.0 V.
A fully integrated analog MPPT technique is proposed to extract maximum power from
the solar cell. This technique does not require Analog to Digital Converter (ADC) and
Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed
MPPT techniques includes a switch capacitor based power sensor which senses current of
boost converter without using any sense resistor. A complete system is designed which
starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output.
low for any electronic circuit to operate. To get rid of this problem, traditionally multiple
solar cells are connected in series to get higher voltage. The disadvantage of this approach
is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can
result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT)
at single solar cell level is the most efficient way to extract power from solar cell.
Power Management IC (MPIC) used to extract power from single solar cell, needs to
start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area
overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an
auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input.
The auxiliary supply powers up a MPPT converter followed by a regulated converter. At
the start up both the converters operate at 100 kHz clock with 80% duty cycle and system
output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up
circuit is turned off and the supply voltage for both the converters is derived from the system
output itself. In steady-state condition the system output is regulated to 3.0 V.
A fully integrated analog MPPT technique is proposed to extract maximum power from
the solar cell. This technique does not require Analog to Digital Converter (ADC) and
Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed
MPPT techniques includes a switch capacitor based power sensor which senses current of
boost converter without using any sense resistor. A complete system is designed which
starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output.
ContributorsSingh, Shrikant (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
Description
Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
ContributorsSingh, Shrikant (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2019