Matching Items (3)
Filtering by

Clear all filters

151945-Thumbnail Image.png
Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
137487-Thumbnail Image.png
Description
The current Enterprise Requirements and Acquisition Model (ERAM), a discrete event simulation of the major tasks and decisions within the DoD acquisition system, identifies several what-if intervention strategies to improve program completion time. However, processes that contribute to the program acquisition completion time were not explicitly identified in the simulation

The current Enterprise Requirements and Acquisition Model (ERAM), a discrete event simulation of the major tasks and decisions within the DoD acquisition system, identifies several what-if intervention strategies to improve program completion time. However, processes that contribute to the program acquisition completion time were not explicitly identified in the simulation study. This research seeks to determine the acquisition processes that contribute significantly to total simulated program time in the acquisition system for all programs reaching Milestone C. Specifically, this research examines the effect of increased scope management, technology maturity, and decreased variation and mean process times in post-Design Readiness Review contractor activities by performing additional simulation analyses. Potential policies are formulated from the results to further improve program acquisition completion time.
ContributorsWorger, Danielle Marie (Author) / Wu, Teresa (Thesis director) / Shunk, Dan (Committee member) / Wirthlin, J. Robert (Committee member) / Industrial, Systems (Contributor) / Barrett, The Honors College (Contributor)
Created2013-05
134430-Thumbnail Image.png
Description
Abstract Chess has been a common research topic for expert-novice studies and thus for learning science as a whole because of its limited framework and longevity as a game. One factor is that chess studies are good at measuring how expert chess players use their memory and skills to approach

Abstract Chess has been a common research topic for expert-novice studies and thus for learning science as a whole because of its limited framework and longevity as a game. One factor is that chess studies are good at measuring how expert chess players use their memory and skills to approach a new chessboard con�guration. Studies have shown that chess skill is based on memory, speci�cally, "chunks" of chess piece positions that have been previously encountered by players. However, debate exists concerning how these chunks are constructed in players' memory. These chunks could be constructed by proximity of pieces on the chessboard as well as their precise location or constructed through attack-defense relations. The primary objective of this study is to support which one is more in line with chess players' actual chess abilities based off their memory, proximity or attack/defense. This study replicates and extends an experiment conducted by McGregor and Howe (2002), which explored the argument that pieces are primed more by attack and defense relations than by proximity. Like their study, the present study examined novice and expert chess players' response times for correct and error responses by showing slides of game configurations. In addition to these metrics, the present study also incorporated an eye-tracker to measure visual attention and EEG to measure affective and cognitive states. They were added to allow the comparison of subtle and unconscious behaviors of both novices and expert chess players. Overall, most McGregor and Howe's (2002) results were replicated supporting their theory on chess expertise. This included statistically significance for skill in the error rates with the mean error rates on the piece recognition tests were 70.1% for novices and 87.9% for experts, as well as significance for the two-way interaction for relatedness and proximity with error rates of 22.4% for unrelated/far, 18.8% for related/far, 15.8% for unrelated
ear, and 29.3% for related
ear. Unfortunately, there were no statistically significance for any of the response time effects, which McGregor and Howe found for the interaction between skill and proximity. Despite eye-tracking and EEG data not either support nor confirm McGregor and Howe's theory on how chess players memorize chessboard configurations, these metrics did help build a secondary theory on how novices typically rely on proximity to approach chess and new visual problems in general. This was exemplified by the statistically significant results for short-term excitement for the two-way interaction of skill and proximity, where the largest short-term excitement score was between novices on near proximity slides. This may indicate that novices, because they may lean toward using proximity to try to recall these pieces, experience a short burst of excitement when the pieces are close to each other because they are more likely to recall these configurations.
ContributorsSeto, Christian Paul (Author) / Atkinson, Robert (Thesis director) / Runger, George (Committee member) / Industrial, Systems (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2017-05